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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [doc/] [sch/] [io_vic_def.sch] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton	`v 20100214 1`
2			`C 1300 300 1 0 0 in_port_vector.sym`
3			`{`
4			`T 1300 300 5 10 1 1 0 6 1 1`
5			`refdes=wdata[7:0]`
6			`}`
7			`C 1300 700 1 0 0 in_port_vector.sym`
8			`{`
9			`T 1300 700 5 10 1 1 0 6 1 1`
10			`refdes=int_in[7:0]`
11			`}`
12			`C 1300 1100 1 0 0 in_port_vector.sym`
13			`{`
14			`T 1300 1100 5 10 1 1 0 6 1 1`
15			`refdes=addr[3:0]`
16			`}`
17			`C 1300 1500 1 0 0 in_port.sym`
18			`{`
19			`T 1300 1500 5 10 1 1 0 6 1 1`
20			`refdes=wr`
21			`}`
22			`C 1300 1900 1 0 0 in_port.sym`
23			`{`
24			`T 1300 1900 5 10 1 1 0 6 1 1`
25			`refdes=reset`
26			`}`
27			`C 1300 2300 1 0 0 in_port.sym`
28			`{`
29			`T 1300 2300 5 10 1 1 0 6 1 1`
30			`refdes=rd`
31			`}`
32			`C 1300 2700 1 0 0 in_port.sym`
33			`{`
34			`T 1300 2700 5 10 1 1 0 6 1 1`
35			`refdes=enable`
36			`}`
37			`C 1300 3100 1 0 0 in_port.sym`
38			`{`
39			`T 1300 3100 5 10 1 1 0 6 1 1`
40			`refdes=cs`
41			`}`
42			`C 1300 3500 1 0 0 in_port.sym`
43			`{`
44			`T 1300 3500 5 10 1 1 0 6 1 1`
45			`refdes=clk`
46			`}`
47			`C 3700 300 1 0 0 out_port_vector.sym`
48			`{`
49			`T 4700 300 5 10 1 1 0 0 1 1`
50			`refdes=vector[7:0]`
51			`}`
52			`C 3700 700 1 0 0 out_port_vector.sym`
53			`{`
54			`T 4700 700 5 10 1 1 0 0 1 1`
55			`refdes=rdata[7:0]`
56			`}`
57			`C 3700 1100 1 0 0 out_port.sym`
58			`{`
59			`T 4700 1100 5 10 1 1 0 0 1 1`
60			`refdes=irq_out`
61			`}`