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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ext_mem_interface/] [rtl/] [xml/] [io_ext_mem_interface_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_ext_mem_interface
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
mb
   
   
   little
   8
     
 
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
 
        
         cs
         
         cs
         
       
 
 
      
  
 
 
 
 
 
 
 
 
 
mem
   
   
     
     
 
        
         addr
         
         mem_addr
           130
         
       
 
        
         cs
         
         mem_cs
         
       
 
 
        
         rdata
         
         mem_rdata
           150
         
       
 
 
 
        
         wdata
         
         mem_wdata
           150
         
       
 
 
        
         rd
         
         mem_rd
         
       
 
        
         wr
         
         mem_wr
         
       
 
 
        
         wait
         
         mem_wait
         
       
 
 
      
  
 
 
 
 
 
 
 
 
ext
   
   
   
     
 
        
         addr
         
         ext_add
           reg
           231
         
       
 
 
        
         wdata
         
         ext_wdata
           reg
           150
         
       
 
 
        
         rdata
         
         ext_rdata
           wire
           150
         
       
 
 
        
         rd
         
         ext_rd
           reg
         
       
 
 
        
         wr
         
         ext_wr
           reg
         
       
 
 
        
         wait
         
         ext_wait
           wire
         
       
 
 
        
         cs
         
         ext_cs
           reg
           10
         
       
 
 
 
      
  
 
 
 
 
 

 
 

 
 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
      
        mb
        ../verilog/io_ext_mem_interface_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
   
        mb
        ../verilog/io_ext_mem_interface_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
  
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_ext_mem_interface"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

 
enable
wire
in

 
 
 
 
wait_st
wire
out
70

 
 
 
 
 
 
bank
wire
out
70

 
 
 
 
 
 
 
ext_ub
reg
out

 
ext_stb
reg
out

 
 
 
ext_lb
reg
out

 
 
 

 

 
 
 
 
 
 

 

 mb
 8
 
   mb
   0x0
   
    ext_mem
    0x10
    8
     
     bank
     0x2
     8
     read-write
     
     
     wait_st
     0x0
     8
     read-write
     
    
   

 
 
 

 mem
 8
 
   mem
   0x0
   
    mem
    0x4000
    16
    
   

 
 
 
 
 
 
 
 

 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ext_mem_interface/] [rtl/] [xml/] [io_ext_mem_interface_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_ext_mem_interface`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72
73			`mb`
74
75
76			`little`
77			`8`
78
79
80
81
82			`rdata`
83
84			`rdata`
85			`wire`
86			`70`
87
88
89
90
91
92			`addr`
93
94			`addr`
95			`30`
96
97
98
99
100			`wdata`
101
102			`wdata`
103			`70`
104
105
106
107
108
109			`rd`
110
111			`rd`
112
113
114
115
116			`wr`
117
118			`wr`
119
120
121
122
123
124			`cs`
125
126			`cs`
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142			`mem`
143
144
145
146
147
148
149			`addr`
150
151			`mem_addr`
152	133	jt_eaton	`130`
153	131	jt_eaton
154
155
156
157			`cs`
158
159			`mem_cs`
160
161
162
163
164
165			`rdata`
166
167			`mem_rdata`
168			`150`
169
170
171
172
173
174
175			`wdata`
176
177			`mem_wdata`
178			`150`
179
180
181
182
183
184			`rd`
185
186			`mem_rd`
187
188
189
190
191			`wr`
192
193			`mem_wr`
194
195
196
197
198
199			`wait`
200
201			`mem_wait`
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216			`ext`
217
218
219
220
221
222
223			`addr`
224
225			`ext_add`
226			`reg`
227			`231`
228
229
230
231
232
233			`wdata`
234
235			`ext_wdata`
236			`reg`
237			`150`
238
239
240
241
242
243			`rdata`
244
245			`ext_rdata`
246			`wire`
247			`150`
248
249
250
251
252
253			`rd`
254
255			`ext_rd`
256			`reg`
257
258
259
260
261
262			`wr`
263
264			`ext_wr`
265			`reg`
266
267
268
269
270
271			`wait`
272
273			`ext_wait`
274			`wire`
275
276
277
278
279
280			`cs`
281
282			`ext_cs`
283			`reg`
284			`10`
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305	133	jt_eaton
306			`elab_verilog`
307			`102.1`
308			`none`
309			`:Simulation:`
310			`./tools/verilog/elab_verilog`
311
312
313			`configuration`
314			`default`
315
316
317			`dest_dir`
318			`io_ports`
319
320
321
322	131	jt_eaton
323
324
325
326	133	jt_eaton
327
328
329	131	jt_eaton
330			`gen_registers`
331	133	jt_eaton	`102.1`
332	131	jt_eaton	`common`
333			`none`
334			`./tools/regtool/gen_registers`
335
336
337			`bus_intf`
338			`mb`
339
340
341			`dest_dir`
342			`../verilog`
343
344
345
346
347
348			`gen_verilog`
349			`104.0`
350			`none`
351			`common`
352			`./tools/verilog/gen_verilog`
353
354
355			`destination`
356			`top`
357
358
359			`dest_dir`
360			`../verilog`
361
362
363
364
365
366
367
368
369
370
371
372
373
374			`fs-common`
375
376
377
378			`../verilog/top.body`
379			`verilogSourcefragment`
380
381
382
383
384
385			`fs-sim`
386
387
388
389			`../verilog/copyright.v`
390			`verilogSourceinclude`
391
392
393
394			`../verilog/common/top`
395			`verilogSourcemodule`
396
397
398
399
400			`mb`
401			`../verilog/io_ext_mem_interface_def_mb`
402			`verilogSourcemodule`
403
404
405
406
407
408
409
410
411
412			`fs-syn`
413
414
415
416			`../verilog/copyright.v`
417			`verilogSourceinclude`
418
419
420
421
422			`../verilog/common/top`
423			`verilogSourcemodule`
424
425
426
427
428			`mb`
429			`../verilog/io_ext_mem_interface_def_mb`
430			`verilogSourcemodule`
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450			`Hierarchical`
451
452
453			`spirit:library="io"`
454			`spirit:name="io_ext_mem_interface"`
455			`spirit:version="def.design"/>`
456
457
458
459
460			`verilog`
461
462
463			`spirit:library="Testbench"`
464			`spirit:name="toolflow"`
465			`spirit:version="verilog"/>`
466
467
468
469
470
471
472
473
474			`commoncommon`
475
476			`Verilog`
477
478
479			`fs-common`
480
481
482
483
484			`sim:Simulation:`
485
486			`Verilog`
487
488
489			`fs-sim`
490
491
492
493
494
495			`syn:Synthesis:`
496
497			`Verilog`
498
499
500			`fs-syn`
501
502
503
504
505
506
507			`doc`
508
509
510			`spirit:library="Testbench"`
511			`spirit:name="toolflow"`
512			`spirit:version="documentation"/>`
513
514			`:Documentation:`
515			`Verilog`
516
517
518
519
520
521
522
523
524
525
526
527			`enable`
528			`wire`
529			`in`
530
531
532
533
534
535			`wait_st`
536			`wire`
537			`out`
538			`70`
539
540
541
542
543
544
545
546			`bank`
547			`wire`
548			`out`
549			`70`
550
551
552
553
554
555
556
557
558			`ext_ub`
559			`reg`
560			`out`
561
562
563			`ext_stb`
564			`reg`
565			`out`
566
567
568
569
570			`ext_lb`
571			`reg`
572			`out`
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589			`mb`
590			`8`
591
592			`mb`
593			`0x0`
594
595			`ext_mem`
596			`0x10`
597			`8`
598
599			`bank`
600			`0x2`
601			`8`
602			`read-write`
603
604
605			`wait_st`
606			`0x0`
607			`8`
608			`read-write`
609
610
611
612
613
614
615
616
617			`mem`
618			`8`
619
620			`mem`
621			`0x0`
622
623			`mem`
624			`0x4000`
625			`16`
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642