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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_gpio/] [rtl/] [xml/] [io_gpio_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_gpio
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 mb
   
   
   little
   8
     
 
     
 
 
        
         rdata
         
         rdata
           wire
           70
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         addr
         
         addr
           30
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 
 

 
 
 
 

 
 
 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
   
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 

 
 
 
  
 
    
      fs-common
 
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
     
        mb
        ../verilog/io_gpio_def_mb
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
  
 
 
 
 
 

       
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
enable
wire
in

 
 
gpio_0_out
wire
out
70

 
gpio_0_oe
wire
out
70

 
 
 
gpio_0_in
wire
in
70

 
 
gpio_1_out
wire
out
70

 
gpio_1_oe
wire
out
70

 
 
gpio_1_in
wire
in
70

 
 
 

 

 
 
 
 
 


 
8
 mb

 mb
 0x0000
 
  
  mb_microbus
  0x10
  8
 
 
 
   gpio_0_out
   0x2
   8
   read-write
  
 
 
   gpio_0_oe
   0x1
   8
   read-write
  
 
 
   gpio_0_in
   0x0
   8
   read-only
  
 
 
 
   gpio_1_out
   0x6
   8
   read-write
  
 
 
   gpio_1_oe
   0x5
   8
   read-write
  
 
 
   gpio_1_in
   0x4
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_gpio/] [rtl/] [xml/] [io_gpio_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_gpio`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70			`mb`
71
72
73			`little`
74			`8`
75
76
77
78
79
80
81			`rdata`
82
83			`rdata`
84			`wire`
85			`70`
86
87
88
89
90
91			`wdata`
92
93			`wdata`
94			`70`
95
96
97
98
99
100			`addr`
101
102			`addr`
103			`30`
104
105
106
107
108
109			`rd`
110
111			`rd`
112
113
114
115
116			`wr`
117
118			`wr`
119
120
121
122
123			`cs`
124
125			`cs`
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147			`gen_registers`
148	133	jt_eaton	`102.1`
149	131	jt_eaton	`common`
150			`none`
151			`./tools/regtool/gen_registers`
152
153
154			`bus_intf`
155			`mb`
156
157
158			`dest_dir`
159			`../verilog`
160
161
162
163
164	133	jt_eaton
165			`elab_verilog`
166			`102.1`
167			`none`
168			`:Simulation:`
169			`./tools/verilog/elab_verilog`
170
171
172			`dest_dir`
173			`io_ports`
174
175
176
177	131	jt_eaton
178	133	jt_eaton
179
180
181
182
183
184	131	jt_eaton
185			`gen_verilog`
186			`104.0`
187			`none`
188			`common`
189			`./tools/verilog/gen_verilog`
190
191
192			`destination`
193			`top`
194
195
196			`dest_dir`
197			`../verilog`
198
199
200
201
202
203
204
205
206
207
208
209
210			`fs-common`
211
212
213
214
215			`../verilog/top.body`
216			`verilogSourcefragment`
217
218
219
220
221
222
223			`fs-sim`
224
225
226
227			`../verilog/copyright.v`
228			`verilogSourceinclude`
229
230
231
232
233			`../verilog/common/top`
234			`verilogSourcemodule`
235
236
237
238
239			`mb`
240			`../verilog/io_gpio_def_mb`
241			`verilogSourcemodule`
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261	133	jt_eaton
262	131	jt_eaton
263			`verilog`
264
265
266			`spirit:library="Testbench"`
267			`spirit:name="toolflow"`
268			`spirit:version="verilog"/>`
269
270
271
272
273
274
275
276
277			`commoncommon`
278
279			`Verilog`
280
281
282			`fs-common`
283
284
285
286
287			`sim:Simulation:`
288			`Verilog`
289
290
291			`fs-sim`
292
293
294
295
296			`syn:Synthesis:`
297			`Verilog`
298
299
300			`fs-sim`
301
302
303
304
305
306			`doc`
307
308
309			`spirit:library="Testbench"`
310			`spirit:name="toolflow"`
311			`spirit:version="documentation"/>`
312
313			`:Documentation:`
314			`Verilog`
315
316
317
318
319
320
321
322
323
324
325
326
327			`enable`
328			`wire`
329			`in`
330
331
332
333			`gpio_0_out`
334			`wire`
335			`out`
336			`70`
337
338
339			`gpio_0_oe`
340			`wire`
341			`out`
342			`70`
343
344
345
346
347			`gpio_0_in`
348			`wire`
349			`in`
350			`70`
351
352
353
354			`gpio_1_out`
355			`wire`
356			`out`
357			`70`
358
359
360			`gpio_1_oe`
361			`wire`
362			`out`
363			`70`
364
365
366
367			`gpio_1_in`
368			`wire`
369			`in`
370			`70`
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386			`8`
387			`mb`
388
389			`mb`
390			`0x0000`
391
392
393			`mb_microbus`
394			`0x10`
395			`8`
396
397
398
399			`gpio_0_out`
400			`0x2`
401			`8`
402			`read-write`
403
404
405
406			`gpio_0_oe`
407			`0x1`
408			`8`
409			`read-write`
410
411
412
413			`gpio_0_in`
414			`0x0`
415			`8`
416			`read-only`
417
418
419
420
421			`gpio_1_out`
422			`0x6`
423			`8`
424			`read-write`
425
426
427
428			`gpio_1_oe`
429			`0x5`
430			`8`
431			`read-write`
432
433
434
435			`gpio_1_in`
436			`0x4`
437			`8`
438			`read-only`
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455