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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_gpio/] [sim/] [testbenches/] [xml/] [io_gpio_def_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_gpio
def_tb
 
 
 
 
 
 

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      io_gpio_def_tb
    
  

 
 
 

 
 
 
 
 
 
 


    BUS_ADDR_WIDTH4

 
 
       
 
              
              Params
              
              
                                   spirit:library="io"
                                   spirit:name="io_gpio"
                                   spirit:version="def_dut.params"/>
              
              
 
 
 
              
              Bfm
              
                                   spirit:library="io"
                                   spirit:name="io_gpio"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              headers
              Verilog
              
              
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 
 

 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.ext
        verilogSourcefragment
      
 
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/common/io_gpio_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/io_gpio_def_tb
        verilogSourcemodule
      
 
 
    
 
 
 
 
 
  
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_gpio`
40			`def_tb`
41
42
43
44
45
46
47
48
49
50
51			`gen_verilog`
52			`104.0`
53			`none`
54			`common`
55			`./tools/verilog/gen_verilog`
56
57
58			`destination`
59	134	jt_eaton	`io_gpio_def_tb`
60	131	jt_eaton
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76			`BUS_ADDR_WIDTH4`
77
78
79
80
81
82
83			`Params`
84
85
86			`spirit:library="io"`
87			`spirit:name="io_gpio"`
88			`spirit:version="def_dut.params"/>`
89
90
91
92
93
94
95			`Bfm`
96
97			`spirit:library="io"`
98			`spirit:name="io_gpio"`
99			`spirit:version="bfm.design"/>`
100
101
102
103
104			`icarus`
105
106
107			`spirit:library="Testbench"`
108			`spirit:name="toolflow"`
109			`spirit:version="icarus"/>`
110
111
112
113
114
115
116
117
118			`headers`
119			`Verilog`
120
121
122
123
124
125			`commoncommon`
126			`Verilog`
127
128
129			`fs-common`
130
131
132
133
134			`sim:Simulation:`
135			`Verilog`
136
137
138			`fs-sim`
139
140
141
142
143
144			`lint:Lint:`
145			`Verilog`
146
147
148			`fs-lint`
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166			`fs-common`
167
168
169
170			`../verilog/top.ext`
171			`verilogSourcefragment`
172
173
174
175
176
177
178
179
180			`fs-sim`
181
182
183
184	134	jt_eaton	`../verilog/common/io_gpio_def_tb`
185	131	jt_eaton	`verilogSourcemodule`
186
187
188
189
190
191
192
193
194			`fs-lint`
195
196
197
198	134	jt_eaton	`../verilog/common/io_gpio_def_tb`
199	131	jt_eaton	`verilogSourcemodule`
200
201
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_gpio/] [sim/] [testbenches/] [xml/] [io_gpio_def_tb.xml] - Blame information for rev 134