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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_module
def  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 slave_enable
  
  
  
    
      
        enable
        enable
      
    
 
 

 

 
 
 
 
 
 

  gen_registers
  103.0
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 

 
   
      fs-common
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
   
 
   
      fs-syn
 
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="def.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

UART_PRESCALE5'b01100
UART_PRE_SIZE5
UART_DIV0
BASE_WIDTH8
ADDR_WIDTH16
NMI_MODE8'h00
IRQ_MODE8'h00

 

 
 
 
 
gpio_0_out
wire
out
70

 
gpio_0_oe
wire
out
70

 
 
 
gpio_0_in
wire
in
70

 
gpio_1_out
wire
out
70

 
gpio_1_oe
wire
out
70

 
 
 
gpio_1_in
wire
in
70

 
timer_irq
wire
out
10

 
pic_irq
wire
out

 
pic_nmi
wire
out

 
pic_irq_in
wire
in
70

 
vic_irq_in
wire
in
70

 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
wire
out

 
tx_irq
wire
out

 
ps2_data_avail
wire
out

 
y_pos
wire
out
90

 
x_pos
wire
out
90

 
new_packet
wire
out

 
ms_mid
wire
out

 
ms_right
wire
out

 
ms_left
wire
out

 
int_out
wire
out

 
vector
wire
out
70

 
 
 
 
ext_ub
wire
out

 
ext_stb
wire
out

 
 
ext_lb
wire
out

 
 
 

 
 

 
 
 
 

 
 
 
   
   8
   mb
 
   
     mb
     0x00
 
     
       gpio
       0x10
       8
 
 

   0_out
   0x02
   8
   read-write
  
 
 
   0_oe
   0x01
   8
   read-write
  
 
 
   0_in
   0x00
   8
   read-only
  
 
 
 
   1_out
   0x06
   8
   read-write
  
 
 
   1_oe
   0x05
   8
   read-write
  
 
 
   1_in
   0x04
   8
   read-only
  
 
 
      
          gpio
          mb
      
 
     
 
 
 
     
       timer
       0x10
       8
 
  
   0_start
   0x00
   8
   read-only
  
 
 
   0_count
   0x02
   8
   read-only
  
 
 
   0_end
   0x04
   8
   write-only
  
 
 
 
   1_start
   0x08
   8
   read-only
  
 
 
   1_count
   0x0a
   8
   read-only
  
 
 
   1_end
   0x0c
   8
   write-only
  
 
 
 
     
          timer
          mb
     
 
     
 
 
     
       uart
       0x10
       8
 
 
   xmit_data
   0x00
   8
   write-only
  
 
 
   rcv_data
   0x02
   8
   read-only
  
 
 
 
   cntrl
   0x04
   8
   read-write
  
 
 
   status
   0x06
   8
   read-only
  
 
 
 
     
          uart
          mb
     
 
     
 
 
 
 
     
       pic
       0x10
       8
 
 
   int_in
   0x00
   8
   read-only
  
 
 
   irq_enable
   0x02
   8
   read-write
  
 
 
   nmi_enable
   0x04
   8
   read-write
  
 
 
 
   irq_act
   0x06
   8
   read-only
  
 
 
   nmi_act
   0x08
   8
   read-only
  
 
 
 
 
 
     
          pic
          mb
     
 
     
 
 
 
 
  
  ps2
  0x10
  8
 
 
 
   data
   0x00
   8
   read-only
  
 
 
 
   wdata_buf
   0x00
   8
   write-only
  
 
 
 
   status
   0x02
   8
   read-only
  
 
 
   cntrl
   0x04
   8
   read-write
  
 
 
 
   x_pos
   0x06
   8
   read-only
  
 
 
   y_pos
   0x08
   8
   read-only
  
 
     
          ps2
          mb
     
 
  
 
 
 
     
       utimer
       0x10
       8
 
 
   latch
   0x00
   8
   read-write
  
 
 
   count
   0x02
   8
   read-write
  
 
 
     
          utimer
          mb
     
 
     
 
 
 
 
     
       vga
       0x10
       8
 
 
   ascii_data
   0x00
   8
   write-only
  
 
 
   add_l
   0x02
   8
   write-only
  
 
 
   add_h
   0x04
   8
   write-only
  
 
 
 
   vadd_l
   0x02
   8
   read-only
  
 
 
   vadd_h
   0x04
   8
   read-only
  
 
 
 
   cntrl
   0x06
   8
   read-write
  
 
 
 
 
 
   char_color
   0x08
   8
   read-write
  
 
 
 
 
   back_color
   0x0a
   8
   read-write
  
 
 
 
   cursor_color
   0x0c
   8
   read-write
  
 
     
          vga
          mb
     
 
     
 
 
 
 
     
       ext_mem
       0x10
       8
 
 
 
   bank
   0x02
   8
   read-write
  
 
 
   wait_st
   0x00
   8
   read-write
  
 
 
 
     
          mem
          mb
     
 
     
 
 
 
 
     
       vic
       0x10
       8
 
 
 
   int_in
   0x00
   8
   read-only
  
 
 
   irq_enable
   0x02
   8
   read-write
  
 
 
 
   irq_act
   0x06
   8
   read-only
  
 
 
   irq_vec
   0x08
   8
   read-only
  
 
 
     
          vic
          mb
     
 
     
 
 
 
 
 
 
   
 
   
 
 
 
 
 
 
 
 
 
 
 
   
 
   17
   ext
 
   
     ext
     0x0000
 
     
       psram
       0x10000
       16
 
     
 
 
   
 
   
 
 
 

 
 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_module`
40			`def default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70			`slave_enable`
71
72
73
74
75
76			`enable`
77			`enable`
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92			`gen_registers`
93			`103.0`
94			`common`
95			`none`
96			`./tools/regtool/gen_registers`
97
98
99			`bus_intf`
100			`mb`
101
102
103			`dest_dir`
104			`../verilog`
105
106
107
108
109
110
111
112			`gen_verilog`
113			`104.0`
114			`none`
115			`common`
116			`./tools/verilog/gen_verilog`
117
118
119			`destination`
120			`top`
121
122
123			`dest_dir`
124			`../verilog`
125
126
127
128
129
130
131
132
133
134
135
136
137			`fs-common`
138
139
140
141			`../verilog/top.rtl`
142			`verilogSourcefragment`
143
144
145
146
147
148
149			`fs-sim`
150
151
152
153			`../verilog/copyright.v`
154			`verilogSourceinclude`
155
156
157
158
159			`../verilog/common/top`
160			`verilogSourcemodule`
161
162
163
164
165
166
167			`fs-syn`
168
169
170
171
172			`../verilog/copyright.v`
173			`verilogSourceinclude`
174
175
176
177
178			`../verilog/common/top`
179			`verilogSourcemodule`
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199			`Hierarchical`
200
201
202			`spirit:library="io"`
203			`spirit:name="io_module"`
204			`spirit:version="def.design"/>`
205
206
207
208			`verilog`
209
210
211			`spirit:library="Testbench"`
212			`spirit:name="toolflow"`
213			`spirit:version="verilog"/>`
214
215
216
217
218
219
220
221
222			`commoncommon`
223			`Verilog`
224
225
226			`fs-common`
227
228
229
230
231			`sim:Simulation:`
232			`Verilog`
233
234
235			`fs-sim`
236
237
238
239
240
241			`syn:Synthesis:`
242			`Verilog`
243
244
245			`fs-syn`
246
247
248
249
250
251
252
253			`doc`
254
255
256			`spirit:library="Testbench"`
257			`spirit:name="toolflow"`
258			`spirit:version="documentation"/>`
259
260			`:Documentation:`
261			`Verilog`
262
263
264
265
266
267
268
269
270
271			`UART_PRESCALE5'b01100`
272			`UART_PRE_SIZE5`
273			`UART_DIV0`
274			`BASE_WIDTH8`
275			`ADDR_WIDTH16`
276			`NMI_MODE8'h00`
277			`IRQ_MODE8'h00`
278
279
280
281
282
283
284
285			`gpio_0_out`
286			`wire`
287			`out`
288			`70`
289
290
291			`gpio_0_oe`
292			`wire`
293			`out`
294			`70`
295
296
297
298
299			`gpio_0_in`
300			`wire`
301			`in`
302			`70`
303
304
305			`gpio_1_out`
306			`wire`
307			`out`
308			`70`
309
310
311			`gpio_1_oe`
312			`wire`
313			`out`
314			`70`
315
316
317
318
319			`gpio_1_in`
320			`wire`
321			`in`
322			`70`
323
324
325			`timer_irq`
326			`wire`
327			`out`
328			`10`
329
330
331			`pic_irq`
332			`wire`
333			`out`
334
335
336			`pic_nmi`
337			`wire`
338			`out`
339
340
341			`pic_irq_in`
342			`wire`
343			`in`
344			`70`
345
346
347			`vic_irq_in`
348			`wire`
349			`in`
350			`70`
351
352
353
354			`cts_pad_in`
355			`wire`
356			`in`
357
358
359			`rts_pad_out`
360			`wire`
361			`out`
362
363
364			`rx_irq`
365			`wire`
366			`out`
367
368
369			`tx_irq`
370			`wire`
371			`out`
372
373
374			`ps2_data_avail`
375			`wire`
376			`out`
377
378
379			`y_pos`
380			`wire`
381			`out`
382			`90`
383
384
385			`x_pos`
386			`wire`
387			`out`
388			`90`
389
390
391			`new_packet`
392			`wire`
393			`out`
394
395
396			`ms_mid`
397			`wire`
398			`out`
399
400
401			`ms_right`
402			`wire`
403			`out`
404
405
406			`ms_left`
407			`wire`
408			`out`
409
410
411			`int_out`
412			`wire`
413			`out`
414
415
416			`vector`
417			`wire`
418			`out`
419			`70`
420
421
422
423
424
425			`ext_ub`
426			`wire`
427			`out`
428
429
430			`ext_stb`
431			`wire`
432			`out`
433
434
435
436			`ext_lb`
437			`wire`
438			`out`
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456			`8`
457			`mb`
458
459
460			`mb`
461			`0x00`
462
463
464			`gpio`
465			`0x10`
466			`8`
467
468
469
470			`0_out`
471			`0x02`
472			`8`
473			`read-write`
474
475
476
477			`0_oe`
478			`0x01`
479			`8`
480			`read-write`
481
482
483
484			`0_in`
485			`0x00`
486			`8`
487			`read-only`
488
489
490
491
492			`1_out`
493			`0x06`
494			`8`
495			`read-write`
496
497
498
499			`1_oe`
500			`0x05`
501			`8`
502			`read-write`
503
504
505
506			`1_in`
507			`0x04`
508			`8`
509			`read-only`
510
511
512
513
514			`gpio`
515			`mb`
516
517
518
519
520
521
522
523			`timer`
524			`0x10`
525			`8`
526
527
528			`0_start`
529			`0x00`
530			`8`
531			`read-only`
532
533
534
535			`0_count`
536			`0x02`
537			`8`
538			`read-only`
539
540
541
542			`0_end`
543			`0x04`
544			`8`
545			`write-only`
546
547
548
549
550			`1_start`
551			`0x08`
552			`8`
553			`read-only`
554
555
556
557			`1_count`
558			`0x0a`
559			`8`
560			`read-only`
561
562
563
564			`1_end`
565			`0x0c`
566			`8`
567			`write-only`
568
569
570
571
572
573			`timer`
574			`mb`
575
576
577
578
579
580
581			`uart`
582			`0x10`
583			`8`
584
585
586			`xmit_data`
587			`0x00`
588			`8`
589			`write-only`
590
591
592
593			`rcv_data`
594			`0x02`
595			`8`
596			`read-only`
597
598
599
600
601			`cntrl`
602			`0x04`
603			`8`
604			`read-write`
605
606
607
608			`status`
609			`0x06`
610			`8`
611			`read-only`
612
613
614
615
616
617			`uart`
618			`mb`
619
620
621
622
623
624
625
626
627			`pic`
628			`0x10`
629			`8`
630
631
632			`int_in`
633			`0x00`
634			`8`
635			`read-only`
636
637
638
639			`irq_enable`
640			`0x02`
641			`8`
642			`read-write`
643
644
645
646			`nmi_enable`
647			`0x04`
648			`8`
649			`read-write`
650
651
652
653
654			`irq_act`
655			`0x06`
656			`8`
657			`read-only`
658
659
660
661			`nmi_act`
662			`0x08`
663			`8`
664			`read-only`
665
666
667
668
669
670
671
672			`pic`
673			`mb`
674
675
676
677
678
679
680
681
682			`ps2`
683			`0x10`
684			`8`
685
686
687
688			`data`
689			`0x00`
690			`8`
691			`read-only`
692
693
694
695
696			`wdata_buf`
697			`0x00`
698			`8`
699			`write-only`
700
701
702
703
704			`status`
705			`0x02`
706			`8`
707			`read-only`
708
709
710
711			`cntrl`
712			`0x04`
713			`8`
714			`read-write`
715
716
717
718
719			`x_pos`
720			`0x06`
721			`8`
722			`read-only`
723
724
725
726			`y_pos`
727			`0x08`
728			`8`
729			`read-only`
730
731
732
733			`ps2`
734			`mb`
735
736
737
738
739
740
741
742			`utimer`
743			`0x10`
744			`8`
745
746
747			`latch`
748			`0x00`
749			`8`
750			`read-write`
751
752
753
754			`count`
755			`0x02`
756			`8`
757			`read-write`
758
759
760
761
762			`utimer`
763			`mb`
764
765
766
767
768
769
770
771
772			`vga`
773			`0x10`
774			`8`
775
776
777			`ascii_data`
778			`0x00`
779			`8`
780			`write-only`
781
782
783
784			`add_l`
785			`0x02`
786			`8`
787			`write-only`
788
789
790
791			`add_h`
792			`0x04`
793			`8`
794			`write-only`
795
796
797
798
799			`vadd_l`
800			`0x02`
801			`8`
802			`read-only`
803
804
805
806			`vadd_h`
807			`0x04`
808			`8`
809			`read-only`
810
811
812
813
814			`cntrl`
815			`0x06`
816			`8`
817			`read-write`
818
819
820
821
822
823
824			`char_color`
825			`0x08`
826			`8`
827			`read-write`
828
829
830
831
832
833			`back_color`
834			`0x0a`
835			`8`
836			`read-write`
837
838
839
840
841			`cursor_color`
842			`0x0c`
843			`8`
844			`read-write`
845
846
847
848			`vga`
849			`mb`
850
851
852
853
854
855
856
857
858			`ext_mem`
859			`0x10`
860			`8`
861
862
863
864			`bank`
865			`0x02`
866			`8`
867			`read-write`
868
869
870
871			`wait_st`
872			`0x00`
873			`8`
874			`read-write`
875
876
877
878
879
880			`mem`
881			`mb`
882
883
884
885
886
887
888
889
890			`vic`
891			`0x10`
892			`8`
893
894
895
896			`int_in`
897			`0x00`
898			`8`
899			`read-only`
900
901
902
903			`irq_enable`
904			`0x02`
905			`8`
906			`read-write`
907
908
909
910
911			`irq_act`
912			`0x06`
913			`8`
914			`read-only`
915
916
917
918			`irq_vec`
919			`0x08`
920			`8`
921			`read-only`
922
923
924
925
926			`vic`
927			`mb`
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953			`17`
954			`ext`
955
956
957			`ext`
958			`0x0000`
959
960
961			`psram`
962			`0x10000`
963			`16`
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992