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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_module
def  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 slave_enable
  
  
  
    
      
        enable
        enable
      
    
 
 

 

 
 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 

 
   
      fs-common
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
   
 
   
      fs-syn
 
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="def.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

 
 
 
 
gpio_0_out
wire
out
70

 
gpio_0_oe
wire
out
70

 
 
 
gpio_0_in
wire
in
70

 
gpio_1_out
wire
out
70

 
gpio_1_oe
wire
out
70

 
 
 
gpio_1_in
wire
in
70

 
timer_irq
wire
out
10

 
pic_irq
wire
out

 
pic_nmi
wire
out

 
pic_irq_in
wire
in
70

 
vic_irq_in
wire
in
70

 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
wire
out

 
tx_irq
wire
out

 
ps2_data_avail
wire
out

 
y_pos
wire
out
90

 
x_pos
wire
out
90

 
new_packet
wire
out

 
ms_mid
wire
out

 
ms_right
wire
out

 
ms_left
wire
out

 
int_out
wire
out

 
vector
wire
out
70

 
 
 
 
ext_ub
wire
out

 
ext_stb
wire
out

 
 
ext_lb
wire
out

 
 
 

 
 

 
 
 
 

 
 
 
   
   8
   mb
 
   
     mb
     0x00
 
     
       gpio
       0x10
       8
 
 

   0_out
   0x02
   8
   read-write
  
 
 
   0_oe
   0x01
   8
   read-write
  
 
 
   0_in
   0x00
   8
   read-only
  
 
 
 
   1_out
   0x06
   8
   read-write
  
 
 
   1_oe
   0x05
   8
   read-write
  
 
 
   1_in
   0x04
   8
   read-only
  
 
 
      
          gpio
          mb
      
 
     
 
 
 
     
       timer
       0x10
       8
 
  
   0_start
   0x00
   8
   read-only
  
 
 
   0_count
   0x02
   8
   read-only
  
 
 
   0_end
   0x04
   8
   write-only
  
 
 
 
   1_start
   0x08
   8
   read-only
  
 
 
   1_count
   0x0a
   8
   read-only
  
 
 
   1_end
   0x0c
   8
   write-only
  
 
 
 
     
          timer
          mb
     
 
     
 
 
     
       uart
       0x10
       8
 
 
   xmit_data
   0x00
   8
   write-only
  
 
 
   rcv_data
   0x02
   8
   read-only
  
 
 
 
   cntrl
   0x04
   8
   read-write
  
 
 
   status
   0x06
   8
   read-only
  
 
 
 
     
          uart
          mb
     
 
     
 
 
 
 
     
       pic
       0x10
       8
 
 
   int_in
   0x00
   8
   read-only
  
 
 
   irq_enable
   0x02
   8
   read-write
  
 
 
   nmi_enable
   0x04
   8
   read-write
  
 
 
 
   irq_act
   0x06
   8
   read-only
  
 
 
   nmi_act
   0x08
   8
   read-only
  
 
 
 
 
 
     
          pic
          mb
     
 
     
 
 
 
 
  
  ps2
  0x10
  8
 
 
 
   data
   0x00
   8
   read-only
  
 
 
 
   wdata_buf
   0x00
   8
   write-only
  
 
 
 
   status
   0x02
   8
   read-only
  
 
 
   cntrl
   0x04
   8
   read-write
  
 
 
 
   x_pos
   0x06
   8
   read-only
  
 
 
   y_pos
   0x08
   8
   read-only
  
 
     
          ps2
          mb
     
 
  
 
 
 
     
       utimer
       0x10
       8
 
 
   latch
   0x00
   8
   read-write
  
 
 
   count
   0x02
   8
   read-write
  
 
 
     
          utimer
          mb
     
 
     
 
 
 
 
     
       vga
       0x10
       8
 
 
   ascii_data
   0x00
   8
   write-only
  
 
 
   add_l
   0x02
   8
   write-only
  
 
 
   add_h
   0x04
   8
   write-only
  
 
 
 
   vadd_l
   0x02
   8
   read-only
  
 
 
   vadd_h
   0x04
   8
   read-only
  
 
 
 
   cntrl
   0x06
   8
   read-write
  
 
 
 
 
 
   char_color
   0x08
   8
   read-write
  
 
 
 
 
   back_color
   0x0a
   8
   read-write
  
 
 
 
   cursor_color
   0x0c
   8
   read-write
  
 
     
          vga
          mb
     
 
     
 
 
 
 
     
       ext_mem
       0x10
       8
 
 
 
   bank
   0x02
   8
   read-write
  
 
 
   wait_st
   0x00
   8
   read-write
  
 
 
 
     
          mem
          mb
     
 
     
 
 
 
 
     
       vic
       0x10
       8
 
 
 
   int_in
   0x00
   8
   read-only
  
 
 
   irq_enable
   0x02
   8
   read-write
  
 
 
 
   irq_act
   0x06
   8
   read-only
  
 
 
   irq_vec
   0x08
   8
   read-only
  
 
 
     
          vic
          mb
     
 
     
 
 
 
 
 
 
   
 
   
 
 
 
 
 
 
 
 
 
 
 
   
 
   17
   ext
 
   
     ext
     0x0000
 
     
       psram
       0x10000
       16
 
     
 
 
   
 
   
 
 
 

 
 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_module`
40			`def default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70			`slave_enable`
71
72
73
74
75
76			`enable`
77			`enable`
78
79
80
81
82
83
84
85
86
87
88
89	133	jt_eaton
90			`elab_verilog`
91			`102.1`
92			`none`
93			`:Simulation:`
94			`./tools/verilog/elab_verilog`
95
96
97			`configuration`
98			`default`
99
100
101			`dest_dir`
102			`io_ports`
103
104
105
106	131	jt_eaton
107
108	133	jt_eaton
109
110	131	jt_eaton
111			`gen_registers`
112	133	jt_eaton	`102.1`
113	131	jt_eaton	`common`
114			`none`
115			`./tools/regtool/gen_registers`
116
117
118			`bus_intf`
119			`mb`
120
121
122			`dest_dir`
123			`../verilog`
124
125
126
127
128
129
130
131			`gen_verilog`
132			`104.0`
133			`none`
134			`common`
135			`./tools/verilog/gen_verilog`
136
137
138			`destination`
139			`top`
140
141
142			`dest_dir`
143			`../verilog`
144
145
146
147
148
149
150
151
152
153
154
155
156			`fs-common`
157
158
159
160			`../verilog/top.rtl`
161			`verilogSourcefragment`
162
163
164
165
166
167
168			`fs-sim`
169
170
171
172			`../verilog/copyright.v`
173			`verilogSourceinclude`
174
175
176
177
178			`../verilog/common/top`
179			`verilogSourcemodule`
180
181
182
183
184
185
186			`fs-syn`
187
188
189
190
191			`../verilog/copyright.v`
192			`verilogSourceinclude`
193
194
195
196
197			`../verilog/common/top`
198			`verilogSourcemodule`
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218			`Hierarchical`
219
220
221			`spirit:library="io"`
222			`spirit:name="io_module"`
223			`spirit:version="def.design"/>`
224
225
226
227			`verilog`
228
229
230			`spirit:library="Testbench"`
231			`spirit:name="toolflow"`
232			`spirit:version="verilog"/>`
233
234
235
236
237
238
239
240
241			`commoncommon`
242			`Verilog`
243
244
245			`fs-common`
246
247
248
249
250			`sim:Simulation:`
251			`Verilog`
252
253
254			`fs-sim`
255
256
257
258
259
260			`syn:Synthesis:`
261			`Verilog`
262
263
264			`fs-syn`
265
266
267
268
269
270
271
272			`doc`
273
274
275			`spirit:library="Testbench"`
276			`spirit:name="toolflow"`
277			`spirit:version="documentation"/>`
278
279			`:Documentation:`
280			`Verilog`
281
282
283
284
285
286
287
288
289
290
291
292
293
294			`gpio_0_out`
295			`wire`
296			`out`
297			`70`
298
299
300			`gpio_0_oe`
301			`wire`
302			`out`
303			`70`
304
305
306
307
308			`gpio_0_in`
309			`wire`
310			`in`
311			`70`
312
313
314			`gpio_1_out`
315			`wire`
316			`out`
317			`70`
318
319
320			`gpio_1_oe`
321			`wire`
322			`out`
323			`70`
324
325
326
327
328			`gpio_1_in`
329			`wire`
330			`in`
331			`70`
332
333
334			`timer_irq`
335			`wire`
336			`out`
337			`10`
338
339
340			`pic_irq`
341			`wire`
342			`out`
343
344
345			`pic_nmi`
346			`wire`
347			`out`
348
349
350			`pic_irq_in`
351			`wire`
352			`in`
353			`70`
354
355
356			`vic_irq_in`
357			`wire`
358			`in`
359			`70`
360
361
362
363			`cts_pad_in`
364			`wire`
365			`in`
366
367
368			`rts_pad_out`
369			`wire`
370			`out`
371
372
373			`rx_irq`
374			`wire`
375			`out`
376
377
378			`tx_irq`
379			`wire`
380			`out`
381
382
383			`ps2_data_avail`
384			`wire`
385			`out`
386
387
388			`y_pos`
389			`wire`
390			`out`
391			`90`
392
393
394			`x_pos`
395			`wire`
396			`out`
397			`90`
398
399
400			`new_packet`
401			`wire`
402			`out`
403
404
405			`ms_mid`
406			`wire`
407			`out`
408
409
410			`ms_right`
411			`wire`
412			`out`
413
414
415			`ms_left`
416			`wire`
417			`out`
418
419
420			`int_out`
421			`wire`
422			`out`
423
424
425			`vector`
426			`wire`
427			`out`
428			`70`
429
430
431
432
433
434			`ext_ub`
435			`wire`
436			`out`
437
438
439			`ext_stb`
440			`wire`
441			`out`
442
443
444
445			`ext_lb`
446			`wire`
447			`out`
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465			`8`
466			`mb`
467
468
469			`mb`
470			`0x00`
471
472
473			`gpio`
474			`0x10`
475			`8`
476
477
478
479			`0_out`
480			`0x02`
481			`8`
482			`read-write`
483
484
485
486			`0_oe`
487			`0x01`
488			`8`
489			`read-write`
490
491
492
493			`0_in`
494			`0x00`
495			`8`
496			`read-only`
497
498
499
500
501			`1_out`
502			`0x06`
503			`8`
504			`read-write`
505
506
507
508			`1_oe`
509			`0x05`
510			`8`
511			`read-write`
512
513
514
515			`1_in`
516			`0x04`
517			`8`
518			`read-only`
519
520
521
522
523			`gpio`
524			`mb`
525
526
527
528
529
530
531
532			`timer`
533			`0x10`
534			`8`
535
536
537			`0_start`
538			`0x00`
539			`8`
540			`read-only`
541
542
543
544			`0_count`
545			`0x02`
546			`8`
547			`read-only`
548
549
550
551			`0_end`
552			`0x04`
553			`8`
554			`write-only`
555
556
557
558
559			`1_start`
560			`0x08`
561			`8`
562			`read-only`
563
564
565
566			`1_count`
567			`0x0a`
568			`8`
569			`read-only`
570
571
572
573			`1_end`
574			`0x0c`
575			`8`
576			`write-only`
577
578
579
580
581
582			`timer`
583			`mb`
584
585
586
587
588
589
590			`uart`
591			`0x10`
592			`8`
593
594
595			`xmit_data`
596			`0x00`
597			`8`
598			`write-only`
599
600
601
602			`rcv_data`
603			`0x02`
604			`8`
605			`read-only`
606
607
608
609
610			`cntrl`
611			`0x04`
612			`8`
613			`read-write`
614
615
616
617			`status`
618			`0x06`
619			`8`
620			`read-only`
621
622
623
624
625
626			`uart`
627			`mb`
628
629
630
631
632
633
634
635
636			`pic`
637			`0x10`
638			`8`
639
640
641			`int_in`
642			`0x00`
643			`8`
644			`read-only`
645
646
647
648			`irq_enable`
649			`0x02`
650			`8`
651			`read-write`
652
653
654
655			`nmi_enable`
656			`0x04`
657			`8`
658			`read-write`
659
660
661
662
663			`irq_act`
664			`0x06`
665			`8`
666			`read-only`
667
668
669
670			`nmi_act`
671			`0x08`
672			`8`
673			`read-only`
674
675
676
677
678
679
680
681			`pic`
682			`mb`
683
684
685
686
687
688
689
690
691			`ps2`
692			`0x10`
693			`8`
694
695
696
697			`data`
698			`0x00`
699			`8`
700			`read-only`
701
702
703
704
705			`wdata_buf`
706			`0x00`
707			`8`
708			`write-only`
709
710
711
712
713			`status`
714			`0x02`
715			`8`
716			`read-only`
717
718
719
720			`cntrl`
721			`0x04`
722			`8`
723			`read-write`
724
725
726
727
728			`x_pos`
729			`0x06`
730			`8`
731			`read-only`
732
733
734
735			`y_pos`
736			`0x08`
737			`8`
738			`read-only`
739
740
741
742			`ps2`
743			`mb`
744
745
746
747
748
749
750
751			`utimer`
752			`0x10`
753			`8`
754
755
756			`latch`
757			`0x00`
758			`8`
759			`read-write`
760
761
762
763			`count`
764			`0x02`
765			`8`
766			`read-write`
767
768
769
770
771			`utimer`
772			`mb`
773
774
775
776
777
778
779
780
781			`vga`
782			`0x10`
783			`8`
784
785
786			`ascii_data`
787			`0x00`
788			`8`
789			`write-only`
790
791
792
793			`add_l`
794			`0x02`
795			`8`
796			`write-only`
797
798
799
800			`add_h`
801			`0x04`
802			`8`
803			`write-only`
804
805
806
807
808			`vadd_l`
809			`0x02`
810			`8`
811			`read-only`
812
813
814
815			`vadd_h`
816			`0x04`
817			`8`
818			`read-only`
819
820
821
822
823			`cntrl`
824			`0x06`
825			`8`
826			`read-write`
827
828
829
830
831
832
833			`char_color`
834			`0x08`
835			`8`
836			`read-write`
837
838
839
840
841
842			`back_color`
843			`0x0a`
844			`8`
845			`read-write`
846
847
848
849
850			`cursor_color`
851			`0x0c`
852			`8`
853			`read-write`
854
855
856
857			`vga`
858			`mb`
859
860
861
862
863
864
865
866
867			`ext_mem`
868			`0x10`
869			`8`
870
871
872
873			`bank`
874			`0x02`
875			`8`
876			`read-write`
877
878
879
880			`wait_st`
881			`0x00`
882			`8`
883			`read-write`
884
885
886
887
888
889			`mem`
890			`mb`
891
892
893
894
895
896
897
898
899			`vic`
900			`0x10`
901			`8`
902
903
904
905			`int_in`
906			`0x00`
907			`8`
908			`read-only`
909
910
911
912			`irq_enable`
913			`0x02`
914			`8`
915			`read-write`
916
917
918
919
920			`irq_act`
921			`0x06`
922			`8`
923			`read-only`
924
925
926
927			`irq_vec`
928			`0x08`
929			`8`
930			`read-only`
931
932
933
934
935			`vic`
936			`mb`
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962			`17`
963			`ext`
964
965
966			`ext`
967			`0x0000`
968
969
970			`psram`
971			`0x10000`
972			`16`
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001