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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_module
def  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 slave_enable
  
  
  
    
      
        enable
        enable
      
    
 
 

 

 
 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      io_module_def
    
  

 
 
 

 
 

 
   
      fs-common
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_module_def
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
   
 
   
      fs-syn
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_module_def
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
 
 

 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="def.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

 
 
 
 
gpio_0_out
wire
out
70

 
gpio_0_oe
wire
out
70

 
 
 
gpio_0_in
wire
in
70

 
gpio_1_out
wire
out
70

 
gpio_1_oe
wire
out
70

 
 
 
gpio_1_in
wire
in
70

 
timer_irq
wire
out
10

 
pic_irq
wire
out

 
pic_nmi
wire
out

 
pic_irq_in
wire
in
70

 
vic_irq_in
wire
in
70

 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
wire
out

 
tx_irq
wire
out

 
ps2_data_avail
wire
out

 
y_pos
wire
out
90

 
x_pos
wire
out
90

 
new_packet
wire
out

 
ms_mid
wire
out

 
ms_right
wire
out

 
ms_left
wire
out

 
int_out
wire
out

 
vector
wire
out
70

 
 
 
 
ext_ub
wire
out

 
ext_stb
wire
out

 
 
ext_lb
wire
out

 
 
 

 
 

 
 
 
 

 
 
 
   
   8
   mb
 
   
     mb
     0x00
 
     
       gpio
       0x10
       8
 
 

   0_out
   0x02
   8
   read-write
  
 
 
   0_oe
   0x01
   8
   read-write
  
 
 
   0_in
   0x00
   8
   read-only
  
 
 
 
   1_out
   0x06
   8
   read-write
  
 
 
   1_oe
   0x05
   8
   read-write
  
 
 
   1_in
   0x04
   8
   read-only
  
 
 
      
          gpio
          mb
      
 
     
 
 
 
     
       timer
       0x10
       8
 
  
   0_start
   0x00
   8
   read-only
  
 
 
   0_count
   0x02
   8
   read-only
  
 
 
   0_end
   0x04
   8
   write-only
  
 
 
 
   1_start
   0x08
   8
   read-only
  
 
 
   1_count
   0x0a
   8
   read-only
  
 
 
   1_end
   0x0c
   8
   write-only
  
 
 
 
     
          timer
          mb
     
 
     
 
 
     
       uart
       0x10
       8
 
 
   xmit_data
   0x00
   8
   write-only
  
 
 
   rcv_data
   0x02
   8
   read-only
  
 
 
 
   cntrl
   0x04
   8
   read-write
  
 
 
   status
   0x06
   8
   read-only
  
 
 
 
     
          uart
          mb
     
 
     
 
 
 
 
     
       pic
       0x10
       8
 
 
   int_in
   0x00
   8
   read-only
  
 
 
   irq_enable
   0x02
   8
   read-write
  
 
 
   nmi_enable
   0x04
   8
   read-write
  
 
 
 
   irq_act
   0x06
   8
   read-only
  
 
 
   nmi_act
   0x08
   8
   read-only
  
 
 
 
 
 
     
          pic
          mb
     
 
     
 
 
 
 
  
  ps2
  0x10
  8
 
 
 
   data
   0x00
   8
   read-only
  
 
 
 
   wdata_buf
   0x00
   8
   write-only
  
 
 
 
   status
   0x02
   8
   read-only
  
 
 
   cntrl
   0x04
   8
   read-write
  
 
 
 
   x_pos
   0x06
   8
   read-only
  
 
 
   y_pos
   0x08
   8
   read-only
  
 
     
          ps2
          mb
     
 
  
 
 
 
     
       utimer
       0x10
       8
 
 
   latch
   0x00
   8
   read-write
  
 
 
   count
   0x02
   8
   read-write
  
 
 
     
          utimer
          mb
     
 
     
 
 
 
 
     
       vga
       0x10
       8
 
 
   ascii_data
   0x00
   8
   write-only
  
 
 
   add_l
   0x02
   8
   write-only
  
 
 
   add_h
   0x04
   8
   write-only
  
 
 
 
   vadd_l
   0x02
   8
   read-only
  
 
 
   vadd_h
   0x04
   8
   read-only
  
 
 
 
   cntrl
   0x06
   8
   read-write
  
 
 
 
 
 
   char_color
   0x08
   8
   read-write
  
 
 
 
 
   back_color
   0x0a
   8
   read-write
  
 
 
 
   cursor_color
   0x0c
   8
   read-write
  
 
     
          vga
          mb
     
 
     
 
 
 
 
     
       ext_mem
       0x10
       8
 
 
 
   bank
   0x02
   8
   read-write
  
 
 
   wait_st
   0x00
   8
   read-write
  
 
 
 
     
          mem
          mb
     
 
     
 
 
 
 
     
       vic
       0x10
       8
 
 
 
   int_in
   0x00
   8
   read-only
  
 
 
   irq_enable
   0x02
   8
   read-write
  
 
 
 
   irq_act
   0x06
   8
   read-only
  
 
 
   irq_vec
   0x08
   8
   read-only
  
 
 
     
          vic
          mb
     
 
     
 
 
 
 
 
 
   
 
   
 
 
 
 
 
 
 
 
 
 
 
   
 
   17
   ext
 
   
     ext
     0x0000
 
     
       psram
       0x10000
       16
 
     
 
 
   
 
   
 
 
 

 
 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	134	jt_eaton
2	131	jt_eaton
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_module`
40			`def default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70			`slave_enable`
71
72
73
74
75
76			`enable`
77			`enable`
78
79
80
81
82
83
84
85
86
87
88
89
90
91			`gen_registers`
92	133	jt_eaton	`102.1`
93	131	jt_eaton	`common`
94			`none`
95			`./tools/regtool/gen_registers`
96
97
98			`bus_intf`
99			`mb`
100
101
102			`dest_dir`
103			`../verilog`
104
105
106
107
108
109
110
111			`gen_verilog`
112			`104.0`
113			`none`
114			`common`
115			`./tools/verilog/gen_verilog`
116
117
118			`destination`
119	134	jt_eaton	`io_module_def`
120	131	jt_eaton
121
122
123
124
125
126
127
128
129
130
131
132			`fs-common`
133
134
135
136			`../verilog/top.rtl`
137			`verilogSourcefragment`
138
139
140
141
142
143
144			`fs-sim`
145
146
147
148	134	jt_eaton	`../verilog/copyright`
149	131	jt_eaton	`verilogSourceinclude`
150
151
152
153
154	134	jt_eaton	`../verilog/common/io_module_def`
155	131	jt_eaton	`verilogSourcemodule`
156
157
158
159	134	jt_eaton
160
161			`dest_dir`
162			`../views/sim/`
163			`verilogSourcelibraryDir`
164
165
166
167
168	131	jt_eaton
169
170
171			`fs-syn`
172
173
174
175
176	134	jt_eaton	`../verilog/copyright`
177	131	jt_eaton	`verilogSourceinclude`
178
179
180
181
182	134	jt_eaton	`../verilog/common/io_module_def`
183	131	jt_eaton	`verilogSourcemodule`
184
185
186
187	134	jt_eaton
188			`dest_dir`
189			`../views/syn/`
190			`verilogSourcelibraryDir`
191
192
193
194
195	131	jt_eaton
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211			`Hierarchical`
212
213
214			`spirit:library="io"`
215			`spirit:name="io_module"`
216			`spirit:version="def.design"/>`
217
218
219
220			`verilog`
221
222
223			`spirit:library="Testbench"`
224			`spirit:name="toolflow"`
225			`spirit:version="verilog"/>`
226
227
228
229
230
231
232
233
234			`commoncommon`
235			`Verilog`
236
237
238			`fs-common`
239
240
241
242
243			`sim:Simulation:`
244			`Verilog`
245
246
247			`fs-sim`
248
249
250
251
252
253			`syn:Synthesis:`
254			`Verilog`
255
256
257			`fs-syn`
258
259
260
261
262
263
264
265			`doc`
266
267
268			`spirit:library="Testbench"`
269			`spirit:name="toolflow"`
270			`spirit:version="documentation"/>`
271
272			`:Documentation:`
273			`Verilog`
274
275
276
277
278
279
280
281
282
283
284
285
286
287			`gpio_0_out`
288			`wire`
289			`out`
290			`70`
291
292
293			`gpio_0_oe`
294			`wire`
295			`out`
296			`70`
297
298
299
300
301			`gpio_0_in`
302			`wire`
303			`in`
304			`70`
305
306
307			`gpio_1_out`
308			`wire`
309			`out`
310			`70`
311
312
313			`gpio_1_oe`
314			`wire`
315			`out`
316			`70`
317
318
319
320
321			`gpio_1_in`
322			`wire`
323			`in`
324			`70`
325
326
327			`timer_irq`
328			`wire`
329			`out`
330			`10`
331
332
333			`pic_irq`
334			`wire`
335			`out`
336
337
338			`pic_nmi`
339			`wire`
340			`out`
341
342
343			`pic_irq_in`
344			`wire`
345			`in`
346			`70`
347
348
349			`vic_irq_in`
350			`wire`
351			`in`
352			`70`
353
354
355
356			`cts_pad_in`
357			`wire`
358			`in`
359
360
361			`rts_pad_out`
362			`wire`
363			`out`
364
365
366			`rx_irq`
367			`wire`
368			`out`
369
370
371			`tx_irq`
372			`wire`
373			`out`
374
375
376			`ps2_data_avail`
377			`wire`
378			`out`
379
380
381			`y_pos`
382			`wire`
383			`out`
384			`90`
385
386
387			`x_pos`
388			`wire`
389			`out`
390			`90`
391
392
393			`new_packet`
394			`wire`
395			`out`
396
397
398			`ms_mid`
399			`wire`
400			`out`
401
402
403			`ms_right`
404			`wire`
405			`out`
406
407
408			`ms_left`
409			`wire`
410			`out`
411
412
413			`int_out`
414			`wire`
415			`out`
416
417
418			`vector`
419			`wire`
420			`out`
421			`70`
422
423
424
425
426
427			`ext_ub`
428			`wire`
429			`out`
430
431
432			`ext_stb`
433			`wire`
434			`out`
435
436
437
438			`ext_lb`
439			`wire`
440			`out`
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458			`8`
459			`mb`
460
461
462			`mb`
463			`0x00`
464
465
466			`gpio`
467			`0x10`
468			`8`
469
470
471
472			`0_out`
473			`0x02`
474			`8`
475			`read-write`
476
477
478
479			`0_oe`
480			`0x01`
481			`8`
482			`read-write`
483
484
485
486			`0_in`
487			`0x00`
488			`8`
489			`read-only`
490
491
492
493
494			`1_out`
495			`0x06`
496			`8`
497			`read-write`
498
499
500
501			`1_oe`
502			`0x05`
503			`8`
504			`read-write`
505
506
507
508			`1_in`
509			`0x04`
510			`8`
511			`read-only`
512
513
514
515
516			`gpio`
517			`mb`
518
519
520
521
522
523
524
525			`timer`
526			`0x10`
527			`8`
528
529
530			`0_start`
531			`0x00`
532			`8`
533			`read-only`
534
535
536
537			`0_count`
538			`0x02`
539			`8`
540			`read-only`
541
542
543
544			`0_end`
545			`0x04`
546			`8`
547			`write-only`
548
549
550
551
552			`1_start`
553			`0x08`
554			`8`
555			`read-only`
556
557
558
559			`1_count`
560			`0x0a`
561			`8`
562			`read-only`
563
564
565
566			`1_end`
567			`0x0c`
568			`8`
569			`write-only`
570
571
572
573
574
575			`timer`
576			`mb`
577
578
579
580
581
582
583			`uart`
584			`0x10`
585			`8`
586
587
588			`xmit_data`
589			`0x00`
590			`8`
591			`write-only`
592
593
594
595			`rcv_data`
596			`0x02`
597			`8`
598			`read-only`
599
600
601
602
603			`cntrl`
604			`0x04`
605			`8`
606			`read-write`
607
608
609
610			`status`
611			`0x06`
612			`8`
613			`read-only`
614
615
616
617
618
619			`uart`
620			`mb`
621
622
623
624
625
626
627
628
629			`pic`
630			`0x10`
631			`8`
632
633
634			`int_in`
635			`0x00`
636			`8`
637			`read-only`
638
639
640
641			`irq_enable`
642			`0x02`
643			`8`
644			`read-write`
645
646
647
648			`nmi_enable`
649			`0x04`
650			`8`
651			`read-write`
652
653
654
655
656			`irq_act`
657			`0x06`
658			`8`
659			`read-only`
660
661
662
663			`nmi_act`
664			`0x08`
665			`8`
666			`read-only`
667
668
669
670
671
672
673
674			`pic`
675			`mb`
676
677
678
679
680
681
682
683
684			`ps2`
685			`0x10`
686			`8`
687
688
689
690			`data`
691			`0x00`
692			`8`
693			`read-only`
694
695
696
697
698			`wdata_buf`
699			`0x00`
700			`8`
701			`write-only`
702
703
704
705
706			`status`
707			`0x02`
708			`8`
709			`read-only`
710
711
712
713			`cntrl`
714			`0x04`
715			`8`
716			`read-write`
717
718
719
720
721			`x_pos`
722			`0x06`
723			`8`
724			`read-only`
725
726
727
728			`y_pos`
729			`0x08`
730			`8`
731			`read-only`
732
733
734
735			`ps2`
736			`mb`
737
738
739
740
741
742
743
744			`utimer`
745			`0x10`
746			`8`
747
748
749			`latch`
750			`0x00`
751			`8`
752			`read-write`
753
754
755
756			`count`
757			`0x02`
758			`8`
759			`read-write`
760
761
762
763
764			`utimer`
765			`mb`
766
767
768
769
770
771
772
773
774			`vga`
775			`0x10`
776			`8`
777
778
779			`ascii_data`
780			`0x00`
781			`8`
782			`write-only`
783
784
785
786			`add_l`
787			`0x02`
788			`8`
789			`write-only`
790
791
792
793			`add_h`
794			`0x04`
795			`8`
796			`write-only`
797
798
799
800
801			`vadd_l`
802			`0x02`
803			`8`
804			`read-only`
805
806
807
808			`vadd_h`
809			`0x04`
810			`8`
811			`read-only`
812
813
814
815
816			`cntrl`
817			`0x06`
818			`8`
819			`read-write`
820
821
822
823
824
825
826			`char_color`
827			`0x08`
828			`8`
829			`read-write`
830
831
832
833
834
835			`back_color`
836			`0x0a`
837			`8`
838			`read-write`
839
840
841
842
843			`cursor_color`
844			`0x0c`
845			`8`
846			`read-write`
847
848
849
850			`vga`
851			`mb`
852
853
854
855
856
857
858
859
860			`ext_mem`
861			`0x10`
862			`8`
863
864
865
866			`bank`
867			`0x02`
868			`8`
869			`read-write`
870
871
872
873			`wait_st`
874			`0x00`
875			`8`
876			`read-write`
877
878
879
880
881
882			`mem`
883			`mb`
884
885
886
887
888
889
890
891
892			`vic`
893			`0x10`
894			`8`
895
896
897
898			`int_in`
899			`0x00`
900			`8`
901			`read-only`
902
903
904
905			`irq_enable`
906			`0x02`
907			`8`
908			`read-write`
909
910
911
912
913			`irq_act`
914			`0x06`
915			`8`
916			`read-only`
917
918
919
920			`irq_vec`
921			`0x08`
922			`8`
923			`read-only`
924
925
926
927
928			`vic`
929			`mb`
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955			`17`
956			`ext`
957
958
959			`ext`
960			`0x0000`
961
962
963			`psram`
964			`0x10000`
965			`16`
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994