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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_gpio.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_module
gpio  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 

 
 
 
 
 
 

  gen_registers
  103.0
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.gpio
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 

 
   
      fs-common
 
 
      
        
        ../verilog/top.gpio.rtl
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.gpio
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-syn
 
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.gpio
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 

 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="gpio.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

UART_PRESCALE5'b01100
UART_PRE_SIZE5
UART_DIV0
BASE_WIDTH8
ADDR_WIDTH16
NMI_MODE8'h00
IRQ_MODE8'h00
 

 
 
 
 
 

 
 
 
enable
wire
in

 
 
 
 
wait_n
wire
out

 
 
gpio_0_out
wire
out
70

 
gpio_0_oe
wire
out
70

 
 
gpio_0_in
wire
in
70

 
gpio_1_out
wire
out
70

 
gpio_1_oe
wire
out
70

 
 
 
gpio_1_in
wire
in
70

 
timer_irq
wire
out
10

 
pic_irq
wire
out

 
pic_nmi
wire
out

 
pic_irq_in
wire
in
70

 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
wire
out

 
tx_irq
wire
out

 

 
 

 
 


 
8
 mb

 mb
 0x00
 
  
  gpio
  0x10
  8
 
 
 
   0_out
   0x2
   8
   read-write
  
 
 
   0_oe
   0x1
   8
   read-write
  
 
 
   0_in
   0x0
   8
   read-only
  
 
 
 
   1_out
   0x6
   8
   read-write
  
 
 
   1_oe
   0x5
   8
   read-write
  
 
 
   1_in
   0x4
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 
 

 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_gpio.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_module`
40			`gpio default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79			`gen_registers`
80			`103.0`
81			`common`
82			`none`
83			`./tools/regtool/gen_registers`
84
85
86			`bus_intf`
87			`mb`
88
89
90			`dest_dir`
91			`../verilog`
92
93
94
95
96
97
98
99			`gen_verilog`
100			`104.0`
101			`none`
102			`common`
103			`./tools/verilog/gen_verilog`
104
105
106			`destination`
107			`top.gpio`
108
109
110			`dest_dir`
111			`../verilog`
112
113
114
115
116
117
118
119
120
121
122
123
124			`fs-common`
125
126
127
128
129			`../verilog/top.gpio.rtl`
130			`verilogSourcefragment`
131
132
133
134
135
136
137			`fs-sim`
138
139
140
141			`../verilog/copyright.v`
142			`verilogSourceinclude`
143
144
145
146
147			`../verilog/common/top.gpio`
148			`verilogSourcemodule`
149
150
151
152
153
154
155
156			`fs-syn`
157
158
159
160
161			`../verilog/copyright.v`
162			`verilogSourceinclude`
163
164
165
166
167			`../verilog/common/top.gpio`
168			`verilogSourcemodule`
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189			`Hierarchical`
190
191
192			`spirit:library="io"`
193			`spirit:name="io_module"`
194			`spirit:version="gpio.design"/>`
195
196
197
198			`verilog`
199
200
201			`spirit:library="Testbench"`
202			`spirit:name="toolflow"`
203			`spirit:version="verilog"/>`
204
205
206
207
208
209
210
211
212			`commoncommon`
213			`Verilog`
214
215
216			`fs-common`
217
218
219
220
221			`sim:Simulation:`
222			`Verilog`
223
224
225			`fs-sim`
226
227
228
229
230
231			`syn:Synthesis:`
232			`Verilog`
233
234
235			`fs-syn`
236
237
238
239
240
241
242			`doc`
243
244
245			`spirit:library="Testbench"`
246			`spirit:name="toolflow"`
247			`spirit:version="documentation"/>`
248
249			`:Documentation:`
250			`Verilog`
251
252
253
254
255
256
257
258
259
260			`UART_PRESCALE5'b01100`
261			`UART_PRE_SIZE5`
262			`UART_DIV0`
263			`BASE_WIDTH8`
264			`ADDR_WIDTH16`
265			`NMI_MODE8'h00`
266			`IRQ_MODE8'h00`
267
268
269
270
271
272
273
274
275
276
277
278			`enable`
279			`wire`
280			`in`
281
282
283
284
285
286			`wait_n`
287			`wire`
288			`out`
289
290
291
292			`gpio_0_out`
293			`wire`
294			`out`
295			`70`
296
297
298			`gpio_0_oe`
299			`wire`
300			`out`
301			`70`
302
303
304
305			`gpio_0_in`
306			`wire`
307			`in`
308			`70`
309
310
311			`gpio_1_out`
312			`wire`
313			`out`
314			`70`
315
316
317			`gpio_1_oe`
318			`wire`
319			`out`
320			`70`
321
322
323
324
325			`gpio_1_in`
326			`wire`
327			`in`
328			`70`
329
330
331			`timer_irq`
332			`wire`
333			`out`
334			`10`
335
336
337			`pic_irq`
338			`wire`
339			`out`
340
341
342			`pic_nmi`
343			`wire`
344			`out`
345
346
347			`pic_irq_in`
348			`wire`
349			`in`
350			`70`
351
352
353
354			`cts_pad_in`
355			`wire`
356			`in`
357
358
359			`rts_pad_out`
360			`wire`
361			`out`
362
363
364			`rx_irq`
365			`wire`
366			`out`
367
368
369			`tx_irq`
370			`wire`
371			`out`
372
373
374
375
376
377
378
379
380
381
382
383			`8`
384			`mb`
385
386			`mb`
387			`0x00`
388
389
390			`gpio`
391			`0x10`
392			`8`
393
394
395
396			`0_out`
397			`0x2`
398			`8`
399			`read-write`
400
401
402
403			`0_oe`
404			`0x1`
405			`8`
406			`read-write`
407
408
409
410			`0_in`
411			`0x0`
412			`8`
413			`read-only`
414
415
416
417
418			`1_out`
419			`0x6`
420			`8`
421			`read-write`
422
423
424
425			`1_oe`
426			`0x5`
427			`8`
428			`read-write`
429
430
431
432			`1_in`
433			`0x4`
434			`8`
435			`read-only`
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455