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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_gpio.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_module
gpio  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 

 
 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.gpio
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 

 
   
      fs-common
 
 
      
        
        ../verilog/top.gpio.rtl
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.gpio
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-syn
 
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.gpio
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 

 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="gpio.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 

 
 
 
enable
wire
in

 
 
 
 
wait_n
wire
out

 
 
gpio_0_out
wire
out
70

 
gpio_0_oe
wire
out
70

 
 
gpio_0_in
wire
in
70

 
gpio_1_out
wire
out
70

 
gpio_1_oe
wire
out
70

 
 
 
gpio_1_in
wire
in
70

 
timer_irq
wire
out
10

 
pic_irq
wire
out

 
pic_nmi
wire
out

 
pic_irq_in
wire
in
70

 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
wire
out

 
tx_irq
wire
out

 

 
 

 
 


 
8
 mb

 mb
 0x00
 
  
  gpio
  0x10
  8
 
 
 
   0_out
   0x2
   8
   read-write
  
 
 
   0_oe
   0x1
   8
   read-write
  
 
 
   0_in
   0x0
   8
   read-only
  
 
 
 
   1_out
   0x6
   8
   read-write
  
 
 
   1_oe
   0x5
   8
   read-write
  
 
 
   1_in
   0x4
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 
 

 
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_gpio.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_module`
40			`gpio default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72
73
74
75
76	133	jt_eaton
77			`elab_verilog`
78			`102.1`
79			`none`
80			`:Simulation:`
81			`./tools/verilog/elab_verilog`
82
83
84			`configuration`
85			`default`
86
87
88			`dest_dir`
89			`io_ports`
90
91
92
93	131	jt_eaton
94
95	133	jt_eaton
96
97	131	jt_eaton
98			`gen_registers`
99	133	jt_eaton	`102.1`
100	131	jt_eaton	`common`
101			`none`
102			`./tools/regtool/gen_registers`
103
104
105			`bus_intf`
106			`mb`
107
108
109			`dest_dir`
110			`../verilog`
111
112
113
114
115
116
117
118			`gen_verilog`
119			`104.0`
120			`none`
121			`common`
122			`./tools/verilog/gen_verilog`
123
124
125			`destination`
126			`top.gpio`
127
128
129			`dest_dir`
130			`../verilog`
131
132
133
134
135
136
137
138
139
140
141
142
143			`fs-common`
144
145
146
147
148			`../verilog/top.gpio.rtl`
149			`verilogSourcefragment`
150
151
152
153
154
155
156			`fs-sim`
157
158
159
160			`../verilog/copyright.v`
161			`verilogSourceinclude`
162
163
164
165
166			`../verilog/common/top.gpio`
167			`verilogSourcemodule`
168
169
170
171
172
173
174
175			`fs-syn`
176
177
178
179
180			`../verilog/copyright.v`
181			`verilogSourceinclude`
182
183
184
185
186			`../verilog/common/top.gpio`
187			`verilogSourcemodule`
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208			`Hierarchical`
209
210
211			`spirit:library="io"`
212			`spirit:name="io_module"`
213			`spirit:version="gpio.design"/>`
214
215
216
217			`verilog`
218
219
220			`spirit:library="Testbench"`
221			`spirit:name="toolflow"`
222			`spirit:version="verilog"/>`
223
224
225
226
227
228
229
230
231			`commoncommon`
232			`Verilog`
233
234
235			`fs-common`
236
237
238
239
240			`sim:Simulation:`
241			`Verilog`
242
243
244			`fs-sim`
245
246
247
248
249
250			`syn:Synthesis:`
251			`Verilog`
252
253
254			`fs-syn`
255
256
257
258
259
260
261			`doc`
262
263
264			`spirit:library="Testbench"`
265			`spirit:name="toolflow"`
266			`spirit:version="documentation"/>`
267
268			`:Documentation:`
269			`Verilog`
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286			`enable`
287			`wire`
288			`in`
289
290
291
292
293
294			`wait_n`
295			`wire`
296			`out`
297
298
299
300			`gpio_0_out`
301			`wire`
302			`out`
303			`70`
304
305
306			`gpio_0_oe`
307			`wire`
308			`out`
309			`70`
310
311
312
313			`gpio_0_in`
314			`wire`
315			`in`
316			`70`
317
318
319			`gpio_1_out`
320			`wire`
321			`out`
322			`70`
323
324
325			`gpio_1_oe`
326			`wire`
327			`out`
328			`70`
329
330
331
332
333			`gpio_1_in`
334			`wire`
335			`in`
336			`70`
337
338
339			`timer_irq`
340			`wire`
341			`out`
342			`10`
343
344
345			`pic_irq`
346			`wire`
347			`out`
348
349
350			`pic_nmi`
351			`wire`
352			`out`
353
354
355			`pic_irq_in`
356			`wire`
357			`in`
358			`70`
359
360
361
362			`cts_pad_in`
363			`wire`
364			`in`
365
366
367			`rts_pad_out`
368			`wire`
369			`out`
370
371
372			`rx_irq`
373			`wire`
374			`out`
375
376
377			`tx_irq`
378			`wire`
379			`out`
380
381
382
383
384
385
386
387
388
389
390
391			`8`
392			`mb`
393
394			`mb`
395			`0x00`
396
397
398			`gpio`
399			`0x10`
400			`8`
401
402
403
404			`0_out`
405			`0x2`
406			`8`
407			`read-write`
408
409
410
411			`0_oe`
412			`0x1`
413			`8`
414			`read-write`
415
416
417
418			`0_in`
419			`0x0`
420			`8`
421			`read-only`
422
423
424
425
426			`1_out`
427			`0x6`
428			`8`
429			`read-write`
430
431
432
433			`1_oe`
434			`0x5`
435			`8`
436			`read-write`
437
438
439
440			`1_in`
441			`0x4`
442			`8`
443			`read-only`
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463