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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_mouse.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_module
mouse  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 

 
 
 
 
 
 
 

  gen_registers
  103.0
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.mouse
    
    
      dest_dir
      ../verilog
    
  

 
 

 
 

 
   
      fs-common
 
      
        
        ../verilog/top.mouse.rtl
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.mouse
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.mouse
        verilogSourcemodule
      
 
 
 
 
 
   
 
 
 
 

 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="mouse.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

UART_PRESCALE5'b01100
UART_PRE_SIZE5
UART_DIV0
BASE_WIDTH8
ADDR_WIDTH16
NMI_MODE8'h00
IRQ_MODE8'h00
 

 
 
 

 
 
 
enable
wire
in

 
 
 
 
wait_n
wire
out

 
 
gpio_0_out
wire
out
70

 
gpio_0_oe
wire
out
70

 
 
 
gpio_0_in
wire
in
70

 
gpio_1_out
wire
out
70

 
gpio_1_oe
wire
out
70

 
 
 
gpio_1_in
wire
in
70

 
timer_irq
wire
out
10

 
pic_irq
wire
out

 
pic_nmi
wire
out

 
pic_irq_in
wire
in
70

 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
wire
out

 
tx_irq
wire
out

 
ps2_data_avail
wire
out

 
y_pos
wire
out
90

 
x_pos
wire
out
90

 
new_packet
wire
out

 
ms_mid
wire
out

 
ms_right
wire
out

 
ms_left
wire
out

 
 

 
 

 
 
 


 
8
 mb

 mb
 0x00
 
  
  gpio
  0x10
  8
 
 
 
   0_out
   0x2
   8
   read-write
  
 
 
   0_oe
   0x1
   8
   read-write
  
 
 
   0_in
   0x0
   8
   read-only
  
 
 
 
   1_out
   0x6
   8
   read-write
  
 
 
   1_oe
   0x5
   8
   read-write
  
 
 
   1_in
   0x4
   8
   read-only
  
 
 
  
 
 

 

 
 
 

 
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_mouse.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_module`
40			`mouse default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80			`gen_registers`
81			`103.0`
82			`common`
83			`none`
84			`./tools/regtool/gen_registers`
85
86
87			`bus_intf`
88			`mb`
89
90
91			`dest_dir`
92			`../verilog`
93
94
95
96
97
98
99
100			`gen_verilog`
101			`104.0`
102			`none`
103			`common`
104			`./tools/verilog/gen_verilog`
105
106
107			`destination`
108			`top.mouse`
109
110
111			`dest_dir`
112			`../verilog`
113
114
115
116
117
118
119
120
121
122
123
124			`fs-common`
125
126
127
128			`../verilog/top.mouse.rtl`
129			`verilogSourcefragment`
130
131
132
133
134
135
136			`fs-sim`
137
138
139
140			`../verilog/copyright.v`
141			`verilogSourceinclude`
142
143
144
145
146			`../verilog/common/top.mouse`
147			`verilogSourcemodule`
148
149
150
151
152
153
154
155			`fs-syn`
156
157
158
159			`../verilog/copyright.v`
160			`verilogSourceinclude`
161
162
163
164
165			`../verilog/common/top.mouse`
166			`verilogSourcemodule`
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188			`Hierarchical`
189
190
191			`spirit:library="io"`
192			`spirit:name="io_module"`
193			`spirit:version="mouse.design"/>`
194
195
196
197
198			`verilog`
199
200
201			`spirit:library="Testbench"`
202			`spirit:name="toolflow"`
203			`spirit:version="verilog"/>`
204
205
206
207
208
209
210
211
212			`commoncommon`
213			`Verilog`
214
215
216			`fs-common`
217
218
219
220
221			`sim:Simulation:`
222			`Verilog`
223
224
225			`fs-sim`
226
227
228
229
230
231			`syn:Synthesis:`
232			`Verilog`
233
234
235			`fs-syn`
236
237
238
239
240
241			`doc`
242
243
244			`spirit:library="Testbench"`
245			`spirit:name="toolflow"`
246			`spirit:version="documentation"/>`
247
248			`:Documentation:`
249			`Verilog`
250
251
252
253
254
255
256
257
258
259			`UART_PRESCALE5'b01100`
260			`UART_PRE_SIZE5`
261			`UART_DIV0`
262			`BASE_WIDTH8`
263			`ADDR_WIDTH16`
264			`NMI_MODE8'h00`
265			`IRQ_MODE8'h00`
266
267
268
269
270
271
272
273
274
275			`enable`
276			`wire`
277			`in`
278
279
280
281
282
283			`wait_n`
284			`wire`
285			`out`
286
287
288
289			`gpio_0_out`
290			`wire`
291			`out`
292			`70`
293
294
295			`gpio_0_oe`
296			`wire`
297			`out`
298			`70`
299
300
301
302
303			`gpio_0_in`
304			`wire`
305			`in`
306			`70`
307
308
309			`gpio_1_out`
310			`wire`
311			`out`
312			`70`
313
314
315			`gpio_1_oe`
316			`wire`
317			`out`
318			`70`
319
320
321
322
323			`gpio_1_in`
324			`wire`
325			`in`
326			`70`
327
328
329			`timer_irq`
330			`wire`
331			`out`
332			`10`
333
334
335			`pic_irq`
336			`wire`
337			`out`
338
339
340			`pic_nmi`
341			`wire`
342			`out`
343
344
345			`pic_irq_in`
346			`wire`
347			`in`
348			`70`
349
350
351
352			`cts_pad_in`
353			`wire`
354			`in`
355
356
357			`rts_pad_out`
358			`wire`
359			`out`
360
361
362			`rx_irq`
363			`wire`
364			`out`
365
366
367			`tx_irq`
368			`wire`
369			`out`
370
371
372			`ps2_data_avail`
373			`wire`
374			`out`
375
376
377			`y_pos`
378			`wire`
379			`out`
380			`90`
381
382
383			`x_pos`
384			`wire`
385			`out`
386			`90`
387
388
389			`new_packet`
390			`wire`
391			`out`
392
393
394			`ms_mid`
395			`wire`
396			`out`
397
398
399			`ms_right`
400			`wire`
401			`out`
402
403
404			`ms_left`
405			`wire`
406			`out`
407
408
409
410
411
412
413
414
415
416
417
418
419
420			`8`
421			`mb`
422
423			`mb`
424			`0x00`
425
426
427			`gpio`
428			`0x10`
429			`8`
430
431
432
433			`0_out`
434			`0x2`
435			`8`
436			`read-write`
437
438
439
440			`0_oe`
441			`0x1`
442			`8`
443			`read-write`
444
445
446
447			`0_in`
448			`0x0`
449			`8`
450			`read-only`
451
452
453
454
455			`1_out`
456			`0x6`
457			`8`
458			`read-write`
459
460
461
462			`1_oe`
463			`0x5`
464			`8`
465			`read-write`
466
467
468
469			`1_in`
470			`0x4`
471			`8`
472			`read-only`
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490