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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_mouse.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_module
mouse  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 

 
 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.mouse
    
    
      dest_dir
      ../verilog
    
  

 
 

 
 

 
   
      fs-common
 
      
        
        ../verilog/top.mouse.rtl
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.mouse
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.mouse
        verilogSourcemodule
      
 
 
 
 
 
   
 
 
 
 

 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="mouse.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 

 
 
 
enable
wire
in

 
 
 
 
wait_n
wire
out

 
 
gpio_0_out
wire
out
70

 
gpio_0_oe
wire
out
70

 
 
 
gpio_0_in
wire
in
70

 
gpio_1_out
wire
out
70

 
gpio_1_oe
wire
out
70

 
 
 
gpio_1_in
wire
in
70

 
timer_irq
wire
out
10

 
pic_irq
wire
out

 
pic_nmi
wire
out

 
pic_irq_in
wire
in
70

 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
wire
out

 
tx_irq
wire
out

 
ps2_data_avail
wire
out

 
y_pos
wire
out
90

 
x_pos
wire
out
90

 
new_packet
wire
out

 
ms_mid
wire
out

 
ms_right
wire
out

 
ms_left
wire
out

 
 

 
 

 
 
 


 
8
 mb

 mb
 0x00
 
  
  gpio
  0x10
  8
 
 
 
   0_out
   0x2
   8
   read-write
  
 
 
   0_oe
   0x1
   8
   read-write
  
 
 
   0_in
   0x0
   8
   read-only
  
 
 
 
   1_out
   0x6
   8
   read-write
  
 
 
   1_oe
   0x5
   8
   read-write
  
 
 
   1_in
   0x4
   8
   read-only
  
 
 
  
 
 

 

 
 
 

 
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_mouse.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	133	jt_eaton
2	131	jt_eaton
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_module`
40			`mouse default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72
73
74
75
76	133	jt_eaton
77			`elab_verilog`
78			`102.1`
79			`none`
80			`:Simulation:`
81			`./tools/verilog/elab_verilog`
82
83
84			`configuration`
85			`default`
86
87
88			`dest_dir`
89			`io_ports`
90
91
92
93	131	jt_eaton
94
95
96	133	jt_eaton
97	131	jt_eaton
98			`gen_registers`
99	133	jt_eaton	`102.1`
100	131	jt_eaton	`common`
101			`none`
102			`./tools/regtool/gen_registers`
103
104
105			`bus_intf`
106			`mb`
107
108
109			`dest_dir`
110			`../verilog`
111
112
113
114
115
116
117
118			`gen_verilog`
119			`104.0`
120			`none`
121			`common`
122			`./tools/verilog/gen_verilog`
123
124
125			`destination`
126			`top.mouse`
127
128
129			`dest_dir`
130			`../verilog`
131
132
133
134
135
136
137
138
139
140
141
142			`fs-common`
143
144
145
146			`../verilog/top.mouse.rtl`
147			`verilogSourcefragment`
148
149
150
151
152
153
154			`fs-sim`
155
156
157
158			`../verilog/copyright.v`
159			`verilogSourceinclude`
160
161
162
163
164			`../verilog/common/top.mouse`
165			`verilogSourcemodule`
166
167
168
169
170
171
172
173			`fs-syn`
174
175
176
177			`../verilog/copyright.v`
178			`verilogSourceinclude`
179
180
181
182
183			`../verilog/common/top.mouse`
184			`verilogSourcemodule`
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206			`Hierarchical`
207
208
209			`spirit:library="io"`
210			`spirit:name="io_module"`
211			`spirit:version="mouse.design"/>`
212
213
214
215
216			`verilog`
217
218
219			`spirit:library="Testbench"`
220			`spirit:name="toolflow"`
221			`spirit:version="verilog"/>`
222
223
224
225
226
227
228
229
230			`commoncommon`
231			`Verilog`
232
233
234			`fs-common`
235
236
237
238
239			`sim:Simulation:`
240			`Verilog`
241
242
243			`fs-sim`
244
245
246
247
248
249			`syn:Synthesis:`
250			`Verilog`
251
252
253			`fs-syn`
254
255
256
257
258
259			`doc`
260
261
262			`spirit:library="Testbench"`
263			`spirit:name="toolflow"`
264			`spirit:version="documentation"/>`
265
266			`:Documentation:`
267			`Verilog`
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283			`enable`
284			`wire`
285			`in`
286
287
288
289
290
291			`wait_n`
292			`wire`
293			`out`
294
295
296
297			`gpio_0_out`
298			`wire`
299			`out`
300			`70`
301
302
303			`gpio_0_oe`
304			`wire`
305			`out`
306			`70`
307
308
309
310
311			`gpio_0_in`
312			`wire`
313			`in`
314			`70`
315
316
317			`gpio_1_out`
318			`wire`
319			`out`
320			`70`
321
322
323			`gpio_1_oe`
324			`wire`
325			`out`
326			`70`
327
328
329
330
331			`gpio_1_in`
332			`wire`
333			`in`
334			`70`
335
336
337			`timer_irq`
338			`wire`
339			`out`
340			`10`
341
342
343			`pic_irq`
344			`wire`
345			`out`
346
347
348			`pic_nmi`
349			`wire`
350			`out`
351
352
353			`pic_irq_in`
354			`wire`
355			`in`
356			`70`
357
358
359
360			`cts_pad_in`
361			`wire`
362			`in`
363
364
365			`rts_pad_out`
366			`wire`
367			`out`
368
369
370			`rx_irq`
371			`wire`
372			`out`
373
374
375			`tx_irq`
376			`wire`
377			`out`
378
379
380			`ps2_data_avail`
381			`wire`
382			`out`
383
384
385			`y_pos`
386			`wire`
387			`out`
388			`90`
389
390
391			`x_pos`
392			`wire`
393			`out`
394			`90`
395
396
397			`new_packet`
398			`wire`
399			`out`
400
401
402			`ms_mid`
403			`wire`
404			`out`
405
406
407			`ms_right`
408			`wire`
409			`out`
410
411
412			`ms_left`
413			`wire`
414			`out`
415
416
417
418
419
420
421
422
423
424
425
426
427
428			`8`
429			`mb`
430
431			`mb`
432			`0x00`
433
434
435			`gpio`
436			`0x10`
437			`8`
438
439
440
441			`0_out`
442			`0x2`
443			`8`
444			`read-write`
445
446
447
448			`0_oe`
449			`0x1`
450			`8`
451			`read-write`
452
453
454
455			`0_in`
456			`0x0`
457			`8`
458			`read-only`
459
460
461
462
463			`1_out`
464			`0x6`
465			`8`
466			`read-write`
467
468
469
470			`1_oe`
471			`0x5`
472			`8`
473			`read-write`
474
475
476
477			`1_in`
478			`0x4`
479			`8`
480			`read-only`
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498