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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_mouse.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_module
mouse  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 

 
 
 
 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      io_module_mouse
    
  

 
 

 
 

 
   
      fs-common
 
      
        
        ../verilog/top.mouse.rtl
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_module_mouse
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
   
 
 
   
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_module_mouse
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
 

 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="mouse.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 

 
 
 
enable
wire
in

 
 
 
 
wait_n
wire
out

 
 
gpio_0_out
wire
out
70

 
gpio_0_oe
wire
out
70

 
 
 
gpio_0_in
wire
in
70

 
gpio_1_out
wire
out
70

 
gpio_1_oe
wire
out
70

 
 
 
gpio_1_in
wire
in
70

 
timer_irq
wire
out
10

 
pic_irq
wire
out

 
pic_nmi
wire
out

 
pic_irq_in
wire
in
70

 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
wire
out

 
tx_irq
wire
out

 
ps2_data_avail
wire
out

 
y_pos
wire
out
90

 
x_pos
wire
out
90

 
new_packet
wire
out

 
ms_mid
wire
out

 
ms_right
wire
out

 
ms_left
wire
out

 
 

 
 

 
 
 


 
8
 mb

 mb
 0x00
 
  
  gpio
  0x10
  8
 
 
 
   0_out
   0x2
   8
   read-write
  
 
 
   0_oe
   0x1
   8
   read-write
  
 
 
   0_in
   0x0
   8
   read-only
  
 
 
 
   1_out
   0x6
   8
   read-write
  
 
 
   1_oe
   0x5
   8
   read-write
  
 
 
   1_in
   0x4
   8
   read-only
  
 
 
  
 
 

 

 
 
 

 
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_mouse.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	133	jt_eaton
2	131	jt_eaton
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_module`
40			`mouse default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80			`gen_registers`
81	133	jt_eaton	`102.1`
82	131	jt_eaton	`common`
83			`none`
84			`./tools/regtool/gen_registers`
85
86
87			`bus_intf`
88			`mb`
89
90
91			`dest_dir`
92			`../verilog`
93
94
95
96
97
98
99
100			`gen_verilog`
101			`104.0`
102			`none`
103			`common`
104			`./tools/verilog/gen_verilog`
105
106
107			`destination`
108	134	jt_eaton	`io_module_mouse`
109	131	jt_eaton
110
111
112
113
114
115
116
117
118
119
120			`fs-common`
121
122
123
124			`../verilog/top.mouse.rtl`
125			`verilogSourcefragment`
126
127
128
129
130
131
132			`fs-sim`
133
134
135
136	134	jt_eaton	`../verilog/copyright`
137	131	jt_eaton	`verilogSourceinclude`
138
139
140
141
142	134	jt_eaton	`../verilog/common/io_module_mouse`
143	131	jt_eaton	`verilogSourcemodule`
144
145
146
147	134	jt_eaton
148			`dest_dir`
149			`../views/sim/`
150			`verilogSourcelibraryDir`
151
152
153
154	131	jt_eaton
155
156
157
158			`fs-syn`
159
160
161
162	134	jt_eaton	`../verilog/copyright`
163	131	jt_eaton	`verilogSourceinclude`
164
165
166
167
168	134	jt_eaton	`../verilog/common/io_module_mouse`
169	131	jt_eaton	`verilogSourcemodule`
170
171
172
173	134	jt_eaton
174			`dest_dir`
175			`../views/syn/`
176			`verilogSourcelibraryDir`
177
178	131	jt_eaton
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196			`Hierarchical`
197
198
199			`spirit:library="io"`
200			`spirit:name="io_module"`
201			`spirit:version="mouse.design"/>`
202
203
204
205
206			`verilog`
207
208
209			`spirit:library="Testbench"`
210			`spirit:name="toolflow"`
211			`spirit:version="verilog"/>`
212
213
214
215
216
217
218
219
220			`commoncommon`
221			`Verilog`
222
223
224			`fs-common`
225
226
227
228
229			`sim:Simulation:`
230			`Verilog`
231
232
233			`fs-sim`
234
235
236
237
238
239			`syn:Synthesis:`
240			`Verilog`
241
242
243			`fs-syn`
244
245
246
247
248
249			`doc`
250
251
252			`spirit:library="Testbench"`
253			`spirit:name="toolflow"`
254			`spirit:version="documentation"/>`
255
256			`:Documentation:`
257			`Verilog`
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273			`enable`
274			`wire`
275			`in`
276
277
278
279
280
281			`wait_n`
282			`wire`
283			`out`
284
285
286
287			`gpio_0_out`
288			`wire`
289			`out`
290			`70`
291
292
293			`gpio_0_oe`
294			`wire`
295			`out`
296			`70`
297
298
299
300
301			`gpio_0_in`
302			`wire`
303			`in`
304			`70`
305
306
307			`gpio_1_out`
308			`wire`
309			`out`
310			`70`
311
312
313			`gpio_1_oe`
314			`wire`
315			`out`
316			`70`
317
318
319
320
321			`gpio_1_in`
322			`wire`
323			`in`
324			`70`
325
326
327			`timer_irq`
328			`wire`
329			`out`
330			`10`
331
332
333			`pic_irq`
334			`wire`
335			`out`
336
337
338			`pic_nmi`
339			`wire`
340			`out`
341
342
343			`pic_irq_in`
344			`wire`
345			`in`
346			`70`
347
348
349
350			`cts_pad_in`
351			`wire`
352			`in`
353
354
355			`rts_pad_out`
356			`wire`
357			`out`
358
359
360			`rx_irq`
361			`wire`
362			`out`
363
364
365			`tx_irq`
366			`wire`
367			`out`
368
369
370			`ps2_data_avail`
371			`wire`
372			`out`
373
374
375			`y_pos`
376			`wire`
377			`out`
378			`90`
379
380
381			`x_pos`
382			`wire`
383			`out`
384			`90`
385
386
387			`new_packet`
388			`wire`
389			`out`
390
391
392			`ms_mid`
393			`wire`
394			`out`
395
396
397			`ms_right`
398			`wire`
399			`out`
400
401
402			`ms_left`
403			`wire`
404			`out`
405
406
407
408
409
410
411
412
413
414
415
416
417
418			`8`
419			`mb`
420
421			`mb`
422			`0x00`
423
424
425			`gpio`
426			`0x10`
427			`8`
428
429
430
431			`0_out`
432			`0x2`
433			`8`
434			`read-write`
435
436
437
438			`0_oe`
439			`0x1`
440			`8`
441			`read-write`
442
443
444
445			`0_in`
446			`0x0`
447			`8`
448			`read-only`
449
450
451
452
453			`1_out`
454			`0x6`
455			`8`
456			`read-write`
457
458
459
460			`1_oe`
461			`0x5`
462			`8`
463			`read-write`
464
465
466
467			`1_in`
468			`0x4`
469			`8`
470			`read-only`
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488