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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [verilog/] [top.ext] - Blame information for rev 133

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assign    gpio_0_in         =  gpio_0_out;
assign    gpio_1_in         =  gpio_1_out;
assign    enable            =  1'b1;
assign    reg_mb_cs         =  1'b1;
assign    cts_pad_in        =  1'b0;
assign    uart_rxd_pad_in   =  uart_txd_pad_out;
assign    pic_irq_in        =  {3'h0,ps2_data_avail,tx_irq,rx_irq,timer_irq};
assign    vic_irq_in        =  {3'h0,ps2_data_avail,tx_irq,rx_irq,timer_irq};
 
 
assign STOP = 1'b0;
assign BAD = 1'b0;
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
3			`assign gpio_0_in = gpio_0_out;`
4			`assign gpio_1_in = gpio_1_out;`
5			`assign enable = 1'b1;`
6			`assign reg_mb_cs = 1'b1;`
7			`assign cts_pad_in = 1'b0;`
8			`assign uart_rxd_pad_in = uart_txd_pad_out;`
9			`assign pic_irq_in = {3'h0,ps2_data_avail,tx_irq,rx_irq,timer_irq};`
10			`assign vic_irq_in = {3'h0,ps2_data_avail,tx_irq,rx_irq,timer_irq};`
11
12
13			`assign STOP = 1'b0;`
14			`assign BAD = 1'b0;`
15
16

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [verilog/] [top.ext] - Blame information for rev 133