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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [xml/] [io_module_def_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_module
def_tb
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      io_module_def_tb
    
  

 
 
 

 
 
 
 

 

    PS2_MODEL_CLKCNT8'h7f
    PS2_MODEL_SIZE8
    BUS_ADDR_WIDTH16

 
 
       
 
              
              Params
              
              
                                   ipxact:library="io"
                                   ipxact:name="io_module"
                                   ipxact:version="def_dut.params"/>
             
              
 
              
              Bfm
              
                                   ipxact:library="io"
                                   ipxact:name="io_module"
                                   ipxact:version="bfm.design"/>
              
 
 
              
              Vga
              
                                   ipxact:library="io"
                                   ipxact:name="io_module"
                                   ipxact:version="vga.design"/>
              
 
 
 
 
 
 
              
              Ps2_bfm
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="ps2_model"
                                   ipxact:version="bfm"/>
              
              
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 

 
 
 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
      
        
        ../verilog/top.ext
        verilogSourcefragment
      
 
 
   
 
   
      fs-sim
 
 
      
        
        ../verilog/common/io_module_def_tb
        verilogSourcemodule
      
 
 
 
   
 
   
      fs-lint
 
 
      
        
        ../verilog/common/io_module_def_tb
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 
 
 
 

 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [xml/] [io_module_def_tb.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	133	jt_eaton
2	131	jt_eaton
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_module`
40			`def_tb`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46
47
48	135	jt_eaton
49			`gen_verilog`
50			`104.0`
51			`none`
52			`:common:`
53			`tools/verilog/gen_verilog`
54
55
56			`destination`
57			`io_module_def_tb`
58
59
60
61	131	jt_eaton
62
63
64	135	jt_eaton
65	131	jt_eaton
66
67
68
69	135	jt_eaton
70	131	jt_eaton
71	135	jt_eaton
72			`PS2_MODEL_CLKCNT8'h7f`
73			`PS2_MODEL_SIZE8`
74			`BUS_ADDR_WIDTH16`
75
76	131	jt_eaton
77
78	135	jt_eaton
79	131	jt_eaton
80	135	jt_eaton
81			`Params`
82
83
84			`ipxact:library="io"`
85			`ipxact:name="io_module"`
86			`ipxact:version="def_dut.params"/>`
87
88
89	131	jt_eaton
90	135	jt_eaton
91			`Bfm`
92
93			`ipxact:library="io"`
94			`ipxact:name="io_module"`
95			`ipxact:version="bfm.design"/>`
96
97	131	jt_eaton
98
99	135	jt_eaton
100			`Vga`
101
102			`ipxact:library="io"`
103			`ipxact:name="io_module"`
104			`ipxact:version="vga.design"/>`
105
106	131	jt_eaton
107
108
109
110
111
112	135	jt_eaton
113			`Ps2_bfm`
114
115
116			`ipxact:library="Testbench"`
117			`ipxact:name="ps2_model"`
118			`ipxact:version="bfm"/>`
119
120
121	131	jt_eaton
122
123	135	jt_eaton
124			`icarus`
125
126
127			`ipxact:library="Testbench"`
128			`ipxact:name="toolflow"`
129			`ipxact:version="icarus"/>`
130
131
132	131	jt_eaton
133
134
135
136
137	135	jt_eaton
138			`common:common:`
139			`Verilog`
140
141
142			`fs-common`
143
144
145	131	jt_eaton
146
147
148
149
150
151
152	135	jt_eaton
153			`sim:Simulation:`
154			`Verilog`
155
156
157			`fs-sim`
158
159
160	131	jt_eaton
161	135	jt_eaton
162			`lint:Lint:`
163			`Verilog`
164
165
166			`fs-lint`
167
168
169	131	jt_eaton
170
171	135	jt_eaton
172	131	jt_eaton
173
174
175
176
177
178	135	jt_eaton
179	131	jt_eaton
180
181
182
183
184
185	135	jt_eaton
186	131	jt_eaton
187	135	jt_eaton
188			`fs-common`
189	131	jt_eaton
190	135	jt_eaton
191
192			`../verilog/sram.load`
193			`verilogSourcefragment`
194
195	131	jt_eaton
196	135	jt_eaton
197
198			`../verilog/top.ext`
199			`verilogSourcefragment`
200
201	131	jt_eaton
202
203	135	jt_eaton
204	131	jt_eaton
205	135	jt_eaton
206			`fs-sim`
207	131	jt_eaton
208
209	135	jt_eaton
210
211			`../verilog/common/io_module_def_tb`
212			`verilogSourcemodule`
213
214	131	jt_eaton
215
216
217	135	jt_eaton
218	131	jt_eaton
219	135	jt_eaton
220			`fs-lint`
221	131	jt_eaton
222
223	135	jt_eaton
224
225			`../verilog/common/io_module_def_tb`
226			`verilogSourcemodule`
227
228	131	jt_eaton
229
230	135	jt_eaton
231	131	jt_eaton
232
233
234
235
236	135	jt_eaton
237	131	jt_eaton
238
239
240
241
242
243
244
245	135	jt_eaton
246	131	jt_eaton
247