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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [xml/] [io_module_def_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_module
def_tb
 
 
 

 

  elab_verilog
  103.0
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog

 

  trace_bus
  103.0
  none
  :*Simulation:*
  ./tools/verilog/trace_bus
    
    
      path
      root.dut
    
    
      bus_name
      reg_mb
    
  

 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 

 

    PS2_MODEL_CLKCNT8'h7f
    PS2_MODEL_SIZE8
    BUS_ADDR_WIDTH16

 
 
       
 
              
              Params
              
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="def_dut.params"/>
             
              
 
              
              Bfm
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="bfm.design"/>
              
 
 
              
              Vga
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="vga.design"/>
              
 
 
 
 
 
 
              
              Ps2_bfm
              
              
                                   spirit:library="Testbench"
                                   spirit:name="ps2_model"
                                   spirit:version="bfm"/>
              
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 

 
 
 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
      
        
        ../verilog/top.ext
        verilogSourcefragment
      
 
 
   
 
   
      fs-sim
 
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
   
 
   
      fs-lint
 
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 
 
 
 

 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [xml/] [io_module_def_tb.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_module`
40			`def_tb`
41
42
43
44
45
46
47			`elab_verilog`
48			`103.0`
49			`none`
50			`:Simulation:`
51			`./tools/verilog/elab_verilog`
52
53
54
55			`trace_bus`
56			`103.0`
57			`none`
58			`:Simulation:`
59			`./tools/verilog/trace_bus`
60
61
62			`path`
63			`root.dut`
64
65
66			`bus_name`
67			`reg_mb`
68
69
70
71
72
73
74
75
76
77			`gen_verilog`
78			`104.0`
79			`none`
80			`common`
81			`./tools/verilog/gen_verilog`
82
83
84			`destination`
85			`top.tb`
86
87
88			`dest_dir`
89			`../verilog`
90
91
92			`top`
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107			`PS2_MODEL_CLKCNT8'h7f`
108			`PS2_MODEL_SIZE8`
109			`BUS_ADDR_WIDTH16`
110
111
112
113
114
115
116			`Params`
117
118
119			`spirit:library="io"`
120			`spirit:name="io_module"`
121			`spirit:version="def_dut.params"/>`
122
123
124
125
126			`Bfm`
127
128			`spirit:library="io"`
129			`spirit:name="io_module"`
130			`spirit:version="bfm.design"/>`
131
132
133
134
135			`Vga`
136
137			`spirit:library="io"`
138			`spirit:name="io_module"`
139			`spirit:version="vga.design"/>`
140
141
142
143
144
145
146
147
148			`Ps2_bfm`
149
150
151			`spirit:library="Testbench"`
152			`spirit:name="ps2_model"`
153			`spirit:version="bfm"/>`
154
155
156
157
158
159			`icarus`
160
161
162			`spirit:library="Testbench"`
163			`spirit:name="toolflow"`
164			`spirit:version="icarus"/>`
165
166
167
168
169
170
171
172
173			`commoncommon`
174			`Verilog`
175
176
177			`fs-common`
178
179
180
181
182
183
184
185
186
187
188			`sim:Simulation:`
189			`Verilog`
190
191
192			`fs-sim`
193
194
195
196
197			`lint:Lint:`
198			`Verilog`
199
200
201			`fs-lint`
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223			`fs-common`
224
225
226
227			`../verilog/sram.load`
228			`verilogSourcefragment`
229
230
231
232
233			`../verilog/top.ext`
234			`verilogSourcefragment`
235
236
237
238
239
240
241			`fs-sim`
242
243
244
245
246			`../verilog/common/top.tb`
247			`verilogSourcemodule`
248
249
250
251
252
253
254
255			`fs-lint`
256
257
258
259
260			`../verilog/common/top.tb`
261			`verilogSourcemodule`
262
263
264
265
266
267
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