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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [xml/] [io_module_def_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_module
def_tb
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      io_module_def_tb
    
  

 
 
 

 
 
 
 

 

    PS2_MODEL_CLKCNT8'h7f
    PS2_MODEL_SIZE8
    BUS_ADDR_WIDTH16

 
 
       
 
              
              Params
              
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="def_dut.params"/>
             
              
 
              
              Bfm
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="bfm.design"/>
              
 
 
              
              Vga
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="vga.design"/>
              
 
 
 
 
 
 
              
              Ps2_bfm
              
              
                                   spirit:library="Testbench"
                                   spirit:name="ps2_model"
                                   spirit:version="bfm"/>
              
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 

 
 
 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
      
        
        ../verilog/top.ext
        verilogSourcefragment
      
 
 
   
 
   
      fs-sim
 
 
      
        
        ../verilog/common/io_module_def_tb
        verilogSourcemodule
      
 
 
 
   
 
   
      fs-lint
 
 
      
        
        ../verilog/common/io_module_def_tb
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 
 
 
 

 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [xml/] [io_module_def_tb.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	133	jt_eaton
2	131	jt_eaton
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_module`
40			`def_tb`
41
42
43
44
45
46
47
48
49			`gen_verilog`
50			`104.0`
51			`none`
52			`common`
53			`./tools/verilog/gen_verilog`
54
55
56			`destination`
57	134	jt_eaton	`io_module_def_tb`
58	131	jt_eaton
59
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71
72			`PS2_MODEL_CLKCNT8'h7f`
73			`PS2_MODEL_SIZE8`
74			`BUS_ADDR_WIDTH16`
75
76
77
78
79
80
81			`Params`
82
83
84			`spirit:library="io"`
85			`spirit:name="io_module"`
86			`spirit:version="def_dut.params"/>`
87
88
89
90
91			`Bfm`
92
93			`spirit:library="io"`
94			`spirit:name="io_module"`
95			`spirit:version="bfm.design"/>`
96
97
98
99
100			`Vga`
101
102			`spirit:library="io"`
103			`spirit:name="io_module"`
104			`spirit:version="vga.design"/>`
105
106
107
108
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110
111
112
113			`Ps2_bfm`
114
115
116			`spirit:library="Testbench"`
117			`spirit:name="ps2_model"`
118			`spirit:version="bfm"/>`
119
120
121
122
123
124			`icarus`
125
126
127			`spirit:library="Testbench"`
128			`spirit:name="toolflow"`
129			`spirit:version="icarus"/>`
130
131
132
133
134
135
136
137
138			`commoncommon`
139			`Verilog`
140
141
142			`fs-common`
143
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152
153			`sim:Simulation:`
154			`Verilog`
155
156
157			`fs-sim`
158
159
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161
162			`lint:Lint:`
163			`Verilog`
164
165
166			`fs-lint`
167
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188			`fs-common`
189
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191
192			`../verilog/sram.load`
193			`verilogSourcefragment`
194
195
196
197
198			`../verilog/top.ext`
199			`verilogSourcefragment`
200
201
202
203
204
205
206			`fs-sim`
207
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211	134	jt_eaton	`../verilog/common/io_module_def_tb`
212	131	jt_eaton	`verilogSourcemodule`
213
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220			`fs-lint`
221
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225	134	jt_eaton	`../verilog/common/io_module_def_tb`
226	131	jt_eaton	`verilogSourcemodule`
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