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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [xml/] [io_module_gpio_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_module
gpio_tb
 
 
 

 

  elab_verilog
  103.0
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog

 
 

  trace_bus
  103.0
  none
  :*Simulation:*
  ./tools/verilog/trace_bus
    
    
      path
      root.dut
    
    
      bus_name
      reg_mb
    
  
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.gpio_tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 

 
 
 
 


    BUS_ADDR_WIDTH16

 
 
       
 
 
              
              Params
              
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="gpio_dut.params"/>
 
 
 
 
             
              
 
              
              Bfm
              
                                   spirit:library="io"
                                   spirit:name="io_module"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 
 
 
 

 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/top.ext.gpio
        verilogSourcefragment
      
 
 
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/common/top.gpio_tb
        verilogSourcemodule
      
 
 
   
 
   
      fs-lint
 
 
      
        
        ../verilog/common/top.gpio_tb
        verilogSourcemodule
      
 
 
 
 
   
 
 
 

 
 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [xml/] [io_module_gpio_tb.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_module`
40			`gpio_tb`
41
42
43
44
45
46
47			`elab_verilog`
48			`103.0`
49			`none`
50			`:Simulation:`
51			`./tools/verilog/elab_verilog`
52
53
54
55
56			`trace_bus`
57			`103.0`
58			`none`
59			`:Simulation:`
60			`./tools/verilog/trace_bus`
61
62
63			`path`
64			`root.dut`
65
66
67			`bus_name`
68			`reg_mb`
69
70
71
72
73
74
75
76
77			`gen_verilog`
78			`104.0`
79			`none`
80			`common`
81			`./tools/verilog/gen_verilog`
82
83
84			`destination`
85			`top.gpio_tb`
86
87
88			`dest_dir`
89			`../verilog`
90
91
92			`top`
93
94
95
96
97
98
99
100
101
102
103
104			`BUS_ADDR_WIDTH16`
105
106
107
108
109
110
111
112			`Params`
113
114
115			`spirit:library="io"`
116			`spirit:name="io_module"`
117			`spirit:version="gpio_dut.params"/>`
118
119
120
121
122
123
124
125
126			`Bfm`
127
128			`spirit:library="io"`
129			`spirit:name="io_module"`
130			`spirit:version="bfm.design"/>`
131
132
133
134
135			`icarus`
136
137
138			`spirit:library="Testbench"`
139			`spirit:name="toolflow"`
140			`spirit:version="icarus"/>`
141
142
143
144
145
146
147
148			`commoncommon`
149			`Verilog`
150
151
152			`fs-common`
153
154
155
156
157			`sim:Simulation:`
158			`Verilog`
159
160
161			`fs-sim`
162
163
164
165
166
167			`lint:Lint:`
168			`Verilog`
169
170
171			`fs-lint`
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191			`fs-common`
192
193
194
195			`../verilog/top.ext.gpio`
196			`verilogSourcefragment`
197
198
199
200
201
202
203
204
205			`fs-sim`
206
207
208
209			`../verilog/common/top.gpio_tb`
210			`verilogSourcemodule`
211
212
213
214
215
216
217			`fs-lint`
218
219
220
221
222			`../verilog/common/top.gpio_tb`
223			`verilogSourcemodule`
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240