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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_pic/] [rtl/] [xml/] [io_pic_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_pic
def
 
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
        
      
     
  
 
 
 slave_reset
  
 
      
  
    
      
        reset
        reset
      
    
        
      
  
 
 
 
 
 
mb
   
  
      
   
     
        
         rdata
         
         rdata
           70
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         addr
         
         addr
           30
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
 
      
        
      
   little
   8
       
  
 
 
 
 

 
 
 

 
 
 
 
 
 

  gen_registers
  102.1
  :*common:*
  none
  tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      io_pic_def
    
  

 
 

 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
    
      fs-sim
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_pic_def
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_pic_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 
 
 

       
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

 
enable
wire
in

 
 
clk
wire
in

 
 
reset
wire
in

 
 
cs
wire
in

 
 
rd
wire
in

 
wr
wire
in

 
 
addr
wire
in
30

 
 
wdata
wire
in
70

 
 
rdata
wire
out
70

 
 
 
 
 
irq_out
reg
out

 
nmi_out
reg
out

 
int_in
wire
in
70

 

 

 
 
 
 
 
 
 
 
 


 
mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   int_in
   0x0
   8
   read-only
  
 
 
   irq_enable
   0x2
   8
   read-write
  
 
 
   nmi_enable
   0x4
   8
   read-write
  
 
 
 
   irq_act
   0x6
   8
   read-only
  
 
 
   nmi_act
   0x8
   8
   read-only
  
 
 
 
  
 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_pic/] [rtl/] [xml/] [io_pic_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_pic`
40			`def`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46	135	jt_eaton	`slave_clk`
47
48
49
50
51
52
53			`clk`
54			`clk`
55
56
57
58
59
60
61	131	jt_eaton
62
63	135	jt_eaton	`slave_reset`
64
65
66
67
68
69
70			`reset`
71			`reset`
72
73
74
75
76
77
78	131	jt_eaton
79
80
81
82	135	jt_eaton	`mb`
83
84
85
86
87
88
89			`rdata`
90
91			`rdata`
92			`70`
93
94
95	131	jt_eaton
96
97	135	jt_eaton
98			`wdata`
99
100			`wdata`
101			`70`
102
103
104	131	jt_eaton
105
106	135	jt_eaton
107			`addr`
108
109			`addr`
110			`30`
111
112
113	131	jt_eaton
114
115	135	jt_eaton
116			`rd`
117
118			`rd`
119
120
121	131	jt_eaton
122	135	jt_eaton
123			`wr`
124
125			`wr`
126
127
128	131	jt_eaton
129	135	jt_eaton
130			`cs`
131
132			`cs`
133
134
135	131	jt_eaton
136
137	135	jt_eaton
138
139
140			`little`
141			`8`
142
143
144	131	jt_eaton
145
146
147
148	135	jt_eaton
149	131	jt_eaton
150
151
152	135	jt_eaton
153	131	jt_eaton
154
155
156
157
158
159	135	jt_eaton
160			`gen_registers`
161			`102.1`
162			`:common:`
163			`none`
164			`tools/regtool/gen_registers`
165
166
167			`bus_intf`
168			`mb`
169
170
171			`dest_dir`
172			`../verilog`
173
174
175
176	131	jt_eaton
177	135	jt_eaton
178			`gen_verilog`
179			`104.0`
180			`none`
181			`:common:`
182			`tools/verilog/gen_verilog`
183
184
185			`destination`
186			`io_pic_def`
187
188
189
190	131	jt_eaton
191
192	135	jt_eaton
193	131	jt_eaton
194	135	jt_eaton
195	131	jt_eaton
196	135	jt_eaton
197			`fs-common`
198	131	jt_eaton
199	135	jt_eaton
200
201			`../verilog/top.body`
202			`verilogSourcefragment`
203
204	131	jt_eaton
205	135	jt_eaton
206	131	jt_eaton
207	135	jt_eaton
208			`fs-sim`
209
210
211			`../verilog/copyright.v`
212			`verilogSourceinclude`
213
214	131	jt_eaton
215	135	jt_eaton
216
217			`../verilog/common/io_pic_def`
218			`verilogSourcemodule`
219
220	131	jt_eaton
221	135	jt_eaton
222			`mb`
223			`../verilog/io_pic_def_mb`
224			`verilogSourcemodule`
225
226	131	jt_eaton
227
228
229	135	jt_eaton
230	131	jt_eaton
231
232
233	135	jt_eaton
234	131	jt_eaton
235
236
237
238
239	135	jt_eaton
240
241	131	jt_eaton
242
243	135	jt_eaton
244			`verilog`
245
246
247			`ipxact:library="Testbench"`
248			`ipxact:name="toolflow"`
249			`ipxact:version="verilog"/>`
250
251
252	131	jt_eaton
253
254
255
256
257	135	jt_eaton
258			`common:common:`
259	131	jt_eaton
260	135	jt_eaton	`Verilog`
261
262
263			`fs-common`
264
265
266	131	jt_eaton
267	135	jt_eaton
268			`sim:Simulation:`
269	131	jt_eaton
270	135	jt_eaton	`Verilog`
271
272
273			`fs-sim`
274
275
276	131	jt_eaton
277	135	jt_eaton
278			`syn:Synthesis:`
279	131	jt_eaton
280	135	jt_eaton	`Verilog`
281
282
283			`fs-sim`
284
285
286	131	jt_eaton
287
288	135	jt_eaton
289			`doc`
290
291
292			`ipxact:library="Testbench"`
293			`ipxact:name="toolflow"`
294			`ipxact:version="documentation"/>`
295
296			`:Documentation:`
297			`Verilog`
298
299	131	jt_eaton
300
301
302	135	jt_eaton
303	131	jt_eaton
304
305
306	135	jt_eaton
307	131	jt_eaton
308	135	jt_eaton	`enable`
309			`wire`
310			`in`
311
312	131	jt_eaton
313	135	jt_eaton
314			`clk`
315			`wire`
316			`in`
317
318	131	jt_eaton
319
320	135	jt_eaton	`reset`
321			`wire`
322			`in`
323
324	131	jt_eaton
325
326	135	jt_eaton	`cs`
327			`wire`
328			`in`
329
330	131	jt_eaton
331
332	135	jt_eaton	`rd`
333			`wire`
334			`in`
335
336	131	jt_eaton
337	135	jt_eaton	`wr`
338			`wire`
339			`in`
340
341	131	jt_eaton
342
343	135	jt_eaton	`addr`
344			`wire`
345			`in`
346			`30`
347
348	131	jt_eaton
349
350	135	jt_eaton	`wdata`
351			`wire`
352			`in`
353			`70`
354
355	131	jt_eaton
356
357	135	jt_eaton	`rdata`
358			`wire`
359			`out`
360			`70`
361
362	131	jt_eaton
363
364
365
366
367	135	jt_eaton	`irq_out`
368			`reg`
369			`out`
370
371
372			`nmi_out`
373			`reg`
374			`out`
375
376
377			`int_in`
378			`wire`
379			`in`
380			`70`
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398			`mb`
399			`8`
400
401			`mb`
402			`0x00`
403	131	jt_eaton
404	135	jt_eaton
405			`mb_microbus`
406			`0x10`
407			`8`
408	131	jt_eaton
409
410	135	jt_eaton
411			`int_in`
412			`0x0`
413			`8`
414			`read-only`
415
416	131	jt_eaton
417	135	jt_eaton
418			`irq_enable`
419			`0x2`
420			`8`
421			`read-write`
422
423	131	jt_eaton
424	135	jt_eaton
425			`nmi_enable`
426			`0x4`
427			`8`
428			`read-write`
429
430	131	jt_eaton
431
432	135	jt_eaton
433			`irq_act`
434			`0x6`
435			`8`
436			`read-only`
437
438	131	jt_eaton
439	135	jt_eaton
440			`nmi_act`
441			`0x8`
442			`8`
443			`read-only`
444
445	131	jt_eaton
446
447
448	135	jt_eaton
449	131	jt_eaton
450
451	135	jt_eaton
452	131	jt_eaton
453	135	jt_eaton
454	131	jt_eaton
455
456
457
458
459
460
461
462	135	jt_eaton