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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_pic/] [rtl/] [xml/] [io_pic_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_pic
def  default
 
 
 

 
 slave_clk
  
  
     
 
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
mb
   
   
   little
   8
       
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         addr
         
         addr
           30
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
 
      
  
 
 
 
 

 
 
 

 
 
 
 
 
 
 

  gen_registers
  103.0
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 

 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
    
      fs-sim
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_pic_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 
 
 

       
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

IRQ_MODE8'h00
NMI_MODE8'h00

 

 
enable
wire
in

 
 
 
 
irq_out
reg
out

 
nmi_out
reg
out

 
int_in
wire
in
70

 

 

 
 
 
 
 
 
 
 
 


 
mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   int_in
   0x0
   8
   read-only
  
 
 
   irq_enable
   0x2
   8
   read-write
  
 
 
   nmi_enable
   0x4
   8
   read-write
  
 
 
 
   irq_act
   0x6
   8
   read-only
  
 
 
   nmi_act
   0x8
   8
   read-only
  
 
 
 
  
 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_pic/] [rtl/] [xml/] [io_pic_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_pic`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52
53			`clk`
54			`clk`
55
56
57
58
59
60			`slave_reset`
61
62
63
64
65
66			`reset`
67			`reset`
68
69
70
71
72
73
74
75			`mb`
76
77
78			`little`
79			`8`
80
81
82
83			`rdata`
84
85			`rdata`
86			`wire`
87			`70`
88
89
90
91
92
93			`wdata`
94
95			`wdata`
96			`70`
97
98
99
100
101
102			`addr`
103
104			`addr`
105			`30`
106
107
108
109
110
111			`rd`
112
113			`rd`
114
115
116
117
118			`wr`
119
120			`wr`
121
122
123
124
125			`cs`
126
127			`cs`
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151			`gen_registers`
152			`103.0`
153			`common`
154			`none`
155			`./tools/regtool/gen_registers`
156
157
158			`bus_intf`
159			`mb`
160
161
162			`dest_dir`
163			`../verilog`
164
165
166
167
168
169			`gen_verilog`
170			`104.0`
171			`none`
172			`common`
173			`./tools/verilog/gen_verilog`
174
175
176			`destination`
177			`top`
178
179
180			`dest_dir`
181			`../verilog`
182
183
184
185
186
187
188
189
190
191
192			`fs-common`
193
194
195
196			`../verilog/top.body`
197			`verilogSourcefragment`
198
199
200
201
202
203			`fs-sim`
204
205
206			`../verilog/copyright.v`
207			`verilogSourceinclude`
208
209
210
211
212			`../verilog/common/top`
213			`verilogSourcemodule`
214
215
216
217			`mb`
218			`../verilog/io_pic_def_mb`
219			`verilogSourcemodule`
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239			`verilog`
240
241
242			`spirit:library="Testbench"`
243			`spirit:name="toolflow"`
244			`spirit:version="verilog"/>`
245
246
247
248
249
250
251
252
253			`commoncommon`
254
255			`Verilog`
256
257
258			`fs-common`
259
260
261
262
263			`sim:Simulation:`
264
265			`Verilog`
266
267
268			`fs-sim`
269
270
271
272
273			`syn:Synthesis:`
274
275			`Verilog`
276
277
278			`fs-sim`
279
280
281
282
283
284			`doc`
285
286
287			`spirit:library="Testbench"`
288			`spirit:name="toolflow"`
289			`spirit:version="documentation"/>`
290
291			`:Documentation:`
292			`Verilog`
293
294
295
296
297
298
299
300
301
302			`IRQ_MODE8'h00`
303			`NMI_MODE8'h00`
304
305
306
307
308			`enable`
309			`wire`
310			`in`
311
312
313
314
315
316			`irq_out`
317			`reg`
318			`out`
319
320
321			`nmi_out`
322			`reg`
323			`out`
324
325
326			`int_in`
327			`wire`
328			`in`
329			`70`
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347			`mb`
348			`8`
349
350			`mb`
351			`0x00`
352
353
354			`mb_microbus`
355			`0x10`
356			`8`
357
358
359
360			`int_in`
361			`0x0`
362			`8`
363			`read-only`
364
365
366
367			`irq_enable`
368			`0x2`
369			`8`
370			`read-write`
371
372
373
374			`nmi_enable`
375			`0x4`
376			`8`
377			`read-write`
378
379
380
381
382			`irq_act`
383			`0x6`
384			`8`
385			`read-only`
386
387
388
389			`nmi_act`
390			`0x8`
391			`8`
392			`read-only`
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411