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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_pic/] [rtl/] [xml/] [io_pic_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_pic
def  default
 
 
 

 
 slave_clk
  
  
     
 
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
mb
   
   
   little
   8
       
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         addr
         
         addr
           30
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
 
      
  
 
 
 
 

 
 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 

 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
    
      fs-sim
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_pic_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 
 
 

       
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

IRQ_MODE8'h00
NMI_MODE8'h00

 

 
enable
wire
in

 
 
 
 
irq_out
reg
out

 
nmi_out
reg
out

 
int_in
wire
in
70

 

 

 
 
 
 
 
 
 
 
 


 
mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   int_in
   0x0
   8
   read-only
  
 
 
   irq_enable
   0x2
   8
   read-write
  
 
 
   nmi_enable
   0x4
   8
   read-write
  
 
 
 
   irq_act
   0x6
   8
   read-only
  
 
 
   nmi_act
   0x8
   8
   read-only
  
 
 
 
  
 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_pic/] [rtl/] [xml/] [io_pic_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_pic`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52
53			`clk`
54			`clk`
55
56
57
58
59
60			`slave_reset`
61
62
63
64
65
66			`reset`
67			`reset`
68
69
70
71
72
73
74
75			`mb`
76
77
78			`little`
79			`8`
80
81
82
83			`rdata`
84
85			`rdata`
86			`wire`
87			`70`
88
89
90
91
92
93			`wdata`
94
95			`wdata`
96			`70`
97
98
99
100
101
102			`addr`
103
104			`addr`
105			`30`
106
107
108
109
110
111			`rd`
112
113			`rd`
114
115
116
117
118			`wr`
119
120			`wr`
121
122
123
124
125			`cs`
126
127			`cs`
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145	133	jt_eaton
146			`elab_verilog`
147			`102.1`
148			`none`
149			`:Simulation:`
150			`./tools/verilog/elab_verilog`
151
152
153			`dest_dir`
154			`io_ports`
155
156
157
158	131	jt_eaton
159
160
161
162
163			`gen_registers`
164	133	jt_eaton	`102.1`
165	131	jt_eaton	`common`
166			`none`
167			`./tools/regtool/gen_registers`
168
169
170			`bus_intf`
171			`mb`
172
173
174			`dest_dir`
175			`../verilog`
176
177
178
179
180
181			`gen_verilog`
182			`104.0`
183			`none`
184			`common`
185			`./tools/verilog/gen_verilog`
186
187
188			`destination`
189			`top`
190
191
192			`dest_dir`
193			`../verilog`
194
195
196
197
198
199
200
201
202
203
204			`fs-common`
205
206
207
208			`../verilog/top.body`
209			`verilogSourcefragment`
210
211
212
213
214
215			`fs-sim`
216
217
218			`../verilog/copyright.v`
219			`verilogSourceinclude`
220
221
222
223
224			`../verilog/common/top`
225			`verilogSourcemodule`
226
227
228
229			`mb`
230			`../verilog/io_pic_def_mb`
231			`verilogSourcemodule`
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251			`verilog`
252
253
254			`spirit:library="Testbench"`
255			`spirit:name="toolflow"`
256			`spirit:version="verilog"/>`
257
258
259
260
261
262
263
264
265			`commoncommon`
266
267			`Verilog`
268
269
270			`fs-common`
271
272
273
274
275			`sim:Simulation:`
276
277			`Verilog`
278
279
280			`fs-sim`
281
282
283
284
285			`syn:Synthesis:`
286
287			`Verilog`
288
289
290			`fs-sim`
291
292
293
294
295
296			`doc`
297
298
299			`spirit:library="Testbench"`
300			`spirit:name="toolflow"`
301			`spirit:version="documentation"/>`
302
303			`:Documentation:`
304			`Verilog`
305
306
307
308
309
310
311
312
313
314			`IRQ_MODE8'h00`
315			`NMI_MODE8'h00`
316
317
318
319
320			`enable`
321			`wire`
322			`in`
323
324
325
326
327
328			`irq_out`
329			`reg`
330			`out`
331
332
333			`nmi_out`
334			`reg`
335			`out`
336
337
338			`int_in`
339			`wire`
340			`in`
341			`70`
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359			`mb`
360			`8`
361
362			`mb`
363			`0x00`
364
365
366			`mb_microbus`
367			`0x10`
368			`8`
369
370
371
372			`int_in`
373			`0x0`
374			`8`
375			`read-only`
376
377
378
379			`irq_enable`
380			`0x2`
381			`8`
382			`read-write`
383
384
385
386			`nmi_enable`
387			`0x4`
388			`8`
389			`read-write`
390
391
392
393
394			`irq_act`
395			`0x6`
396			`8`
397			`read-only`
398
399
400
401			`nmi_act`
402			`0x8`
403			`8`
404			`read-only`
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423