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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_pic/] [rtl/] [xml/] [io_pic_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_pic
def  default
 
 
 

 
 slave_clk
  
  
     
 
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
mb
   
   
   little
   8
       
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         addr
         
         addr
           30
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
 
      
  
 
 
 
 

 
 
 

 
 
 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      io_pic_def
    
  

 
 

 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
    
      fs-sim
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_pic_def
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_pic_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 
 
 

       
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

IRQ_MODE8'h00
NMI_MODE8'h00

 

 
enable
wire
in

 
 
 
 
irq_out
reg
out

 
nmi_out
reg
out

 
int_in
wire
in
70

 

 

 
 
 
 
 
 
 
 
 


 
mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   int_in
   0x0
   8
   read-only
  
 
 
   irq_enable
   0x2
   8
   read-write
  
 
 
   nmi_enable
   0x4
   8
   read-write
  
 
 
 
   irq_act
   0x6
   8
   read-only
  
 
 
   nmi_act
   0x8
   8
   read-only
  
 
 
 
  
 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_pic/] [rtl/] [xml/] [io_pic_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_pic`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52
53			`clk`
54			`clk`
55
56
57
58
59
60			`slave_reset`
61
62
63
64
65
66			`reset`
67			`reset`
68
69
70
71
72
73
74
75			`mb`
76
77
78			`little`
79			`8`
80
81
82
83			`rdata`
84
85			`rdata`
86			`wire`
87			`70`
88
89
90
91
92
93			`wdata`
94
95			`wdata`
96			`70`
97
98
99
100
101
102			`addr`
103
104			`addr`
105			`30`
106
107
108
109
110
111			`rd`
112
113			`rd`
114
115
116
117
118			`wr`
119
120			`wr`
121
122
123
124
125			`cs`
126
127			`cs`
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150			`gen_registers`
151	133	jt_eaton	`102.1`
152	131	jt_eaton	`common`
153			`none`
154			`./tools/regtool/gen_registers`
155
156
157			`bus_intf`
158			`mb`
159
160
161			`dest_dir`
162			`../verilog`
163
164
165
166
167
168			`gen_verilog`
169			`104.0`
170			`none`
171			`common`
172			`./tools/verilog/gen_verilog`
173
174
175			`destination`
176	134	jt_eaton	`io_pic_def`
177	131	jt_eaton
178
179
180
181
182
183
184
185
186
187			`fs-common`
188
189
190
191			`../verilog/top.body`
192			`verilogSourcefragment`
193
194
195
196
197
198			`fs-sim`
199
200
201			`../verilog/copyright.v`
202			`verilogSourceinclude`
203
204
205
206
207	134	jt_eaton	`../verilog/common/io_pic_def`
208	131	jt_eaton	`verilogSourcemodule`
209
210
211
212			`mb`
213			`../verilog/io_pic_def_mb`
214			`verilogSourcemodule`
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234			`verilog`
235
236
237			`spirit:library="Testbench"`
238			`spirit:name="toolflow"`
239			`spirit:version="verilog"/>`
240
241
242
243
244
245
246
247
248			`commoncommon`
249
250			`Verilog`
251
252
253			`fs-common`
254
255
256
257
258			`sim:Simulation:`
259
260			`Verilog`
261
262
263			`fs-sim`
264
265
266
267
268			`syn:Synthesis:`
269
270			`Verilog`
271
272
273			`fs-sim`
274
275
276
277
278
279			`doc`
280
281
282			`spirit:library="Testbench"`
283			`spirit:name="toolflow"`
284			`spirit:version="documentation"/>`
285
286			`:Documentation:`
287			`Verilog`
288
289
290
291
292
293
294
295
296
297			`IRQ_MODE8'h00`
298			`NMI_MODE8'h00`
299
300
301
302
303			`enable`
304			`wire`
305			`in`
306
307
308
309
310
311			`irq_out`
312			`reg`
313			`out`
314
315
316			`nmi_out`
317			`reg`
318			`out`
319
320
321			`int_in`
322			`wire`
323			`in`
324			`70`
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342			`mb`
343			`8`
344
345			`mb`
346			`0x00`
347
348
349			`mb_microbus`
350			`0x10`
351			`8`
352
353
354
355			`int_in`
356			`0x0`
357			`8`
358			`read-only`
359
360
361
362			`irq_enable`
363			`0x2`
364			`8`
365			`read-write`
366
367
368
369			`nmi_enable`
370			`0x4`
371			`8`
372			`read-write`
373
374
375
376
377			`irq_act`
378			`0x6`
379			`8`
380			`read-only`
381
382
383
384			`nmi_act`
385			`0x8`
386			`8`
387			`read-only`
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406