OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_pic/] [sim/] [testbenches/] [xml/] [io_pic_def_lint.xml] - Blame information for rev 133

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 131 jt_eaton
2
30
31
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
32
xmlns:socgen="http://opencores.org"
33
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
34
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
35
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
36
 
37
opencores.org
38
io
39
io_pic
40
def_lint
41
 
42 133 jt_eaton
43 131 jt_eaton
 
44 133 jt_eaton
45
  elab_verilog
46
  102.1
47
  none
48
  :*Simulation:*
49
>
50
  ./tools/verilog/elab_verilog
51
    
52
    
53
      configuration
54
      default
55
    
56
    
57
      dest_dir
58
      io_ports
59
    
60
  
61
62 131 jt_eaton
 
63 133 jt_eaton
64
  gen_design
65
  102.1
66
  none
67
  :*Simulation:*
68
>
69
  ./tools/verilog/gen_design
70
    
71
    
72
      dest_dir
73
      io_ports
74
    
75
  
76
77 131 jt_eaton
 
78 133 jt_eaton
79
 
80
 
81
 
82 131 jt_eaton
83
 
84
 
85
       
86
 
87
              
88
              Dut
89
              
90
              
91
                                   spirit:library="io"
92
                                   spirit:name="io_pic"
93
                                   spirit:version="def_dut.params"/>
94
              
95
              
96
 
97
 
98
              
99
              lint
100
              :*Lint:*
101
              Verilog
102
              fs-lint
103
              
104
 
105
 
106
              
107
              rtl_check
108
              
109
              
110
                                   spirit:library="Testbench"
111
                                   spirit:name="toolflow"
112
                                   spirit:version="rtl_check"/>
113
              
114
              
115
 
116
      
117
 
118
 
119
120
 
121
 
122
 
123
 
124
 
125
  
126
 
127
 
128
 
129
    
130
      fs-lint
131
 
132
      
133
        
134
        ../verilog/lint/io_pic_def_lint
135
        verilogSource
136
        module
137
      
138
 
139
 
140
 
141
    
142
 
143
 
144
 
145
 
146
 
147
  
148
 
149
 
150
 
151
 
152

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.