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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [verilog/] [top.body] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton
parameter PS2_DATA      = 4'h0;
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parameter STATUS        = 4'h2;
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parameter CNTRL         = 4'h4;
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`VARIANT`MB
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ps2_micro_reg
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(
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   .clk                ( clk              ),
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   .reset              ( reset            ),
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   .enable             ( enable           ),
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   .cs                 ( cs               ),
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   .wr                 ( wr               ),
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   .rd                 ( rd               ),
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   .addr               ( addr[3:0]        ),
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   .byte_lanes         ( 1'b1             ),
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   .wdata              ( wdata[7:0]       ),
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   .rdata              ( rdata            ),
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   .ps2_data_rdata     ( rcv_data         ),
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   .ps2_data_dec       ( ps2_data_rd      ),
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   .ps2_data_cs    (),
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   .wdata_buf_cs (),
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   .wdata_buf_dec (),
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   .wdata_buf_wr_0 (),
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   .status_cs (),
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   .status_dec (),
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   .cntrl_cs (),
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   .cntrl_dec (),
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   .cntrl_wr_0 (),
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   .status_rdata       ({!buffer_empty   ,
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                          rcv_data_avail ,
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                          busy           ,
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                          rx_parity_error,
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                          rx_parity_rcv  ,
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                          rx_parity_cal  ,
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                          rx_frame_error ,
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                          tx_ack_error }  ),
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   .cntrl              ( cntrl            ),
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   .cntrl_rdata        ( cntrl            ),
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   .next_cntrl         ( cntrl            ),
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   .wdata_buf          ( wdata_buf        ),
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   .next_wdata_buf     ( wdata_buf        )
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);
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always@(posedge clk)
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if (reset)
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  begin
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    ps2_data_read_stb <= 1'b0;
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   end
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else
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  begin
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   ps2_data_read_stb  <= (  enable &&  ps2_data_rd  && rd );
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  end
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assign   ps2_rx_clear      = cntrl[0] ? read :rd && cs && enable && ps2_data_rd;
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assign        poll_enable  =   cntrl[0];
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