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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [xml/] [io_ps2_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_ps2
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 

 
 
 

 
 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_ps2_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
    
      fs-syn
 
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_ps2_def_mb
        verilogSourcemodule
      
 
 
 
 
 
    
 
 
 
 
  
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_ps2"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
 
enable
wire
in

 
 
 
rcv_data_avail
wire
out

 
 
 
 

 

 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   ps2_data
   0x0
   8
   read-only
  
 
 
   wdata_buf
   0x0
   8
   write-only
  
 
 
   status
   0x2
   8
   read-only
  
 
 
   cntrl
   0x4
   8
   read-write
  
 
 
 
 
  
 
 

 

 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [xml/] [io_ps2_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_ps2`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71			`mb`
72
73
74			`little`
75			`8`
76
77
78
79			`rdata`
80
81			`rdata`
82			`wire`
83			`70`
84
85
86
87
88			`addr`
89
90			`addr`
91			`30`
92
93
94
95
96
97			`wdata`
98
99			`wdata`
100			`70`
101
102
103
104
105
106			`rd`
107
108			`rd`
109
110
111
112
113			`wr`
114
115			`wr`
116
117
118
119
120			`cs`
121
122			`cs`
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139	133	jt_eaton
140			`elab_verilog`
141			`102.1`
142			`none`
143			`:Simulation:`
144			`./tools/verilog/elab_verilog`
145
146
147			`dest_dir`
148			`io_ports`
149
150
151
152	131	jt_eaton
153
154
155
156
157			`gen_registers`
158	133	jt_eaton	`102.1`
159	131	jt_eaton	`common`
160			`none`
161			`./tools/regtool/gen_registers`
162
163
164			`bus_intf`
165			`mb`
166
167
168			`dest_dir`
169			`../verilog`
170
171
172
173
174
175
176
177			`gen_verilog`
178			`104.0`
179			`none`
180			`common`
181			`./tools/verilog/gen_verilog`
182
183
184			`destination`
185			`top`
186
187
188			`dest_dir`
189			`../verilog`
190
191
192
193
194
195
196
197
198
199
200
201
202
203			`fs-common`
204
205
206
207			`../verilog/top.body`
208			`verilogSourcefragment`
209
210
211
212
213
214
215			`fs-sim`
216
217
218
219			`../verilog/copyright.v`
220			`verilogSourceinclude`
221
222
223
224
225			`../verilog/common/top`
226			`verilogSourcemodule`
227
228
229
230			`mb`
231			`../verilog/io_ps2_def_mb`
232			`verilogSourcemodule`
233
234
235
236
237
238
239
240
241
242			`fs-syn`
243
244
245
246
247			`../verilog/copyright.v`
248			`verilogSourceinclude`
249
250
251
252
253			`../verilog/common/top`
254			`verilogSourcemodule`
255
256
257
258			`mb`
259			`../verilog/io_ps2_def_mb`
260			`verilogSourcemodule`
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282			`Hierarchical`
283
284
285			`spirit:library="io"`
286			`spirit:name="io_ps2"`
287			`spirit:version="def.design"/>`
288
289
290
291
292			`verilog`
293
294
295			`spirit:library="Testbench"`
296			`spirit:name="toolflow"`
297			`spirit:version="verilog"/>`
298
299
300
301
302
303
304
305
306			`commoncommon`
307			`Verilog`
308
309
310			`fs-common`
311
312
313
314
315			`sim:Simulation:`
316			`Verilog`
317
318
319			`fs-sim`
320
321
322
323
324
325			`syn:Synthesis:`
326			`Verilog`
327
328
329			`fs-syn`
330
331
332
333
334
335			`doc`
336
337
338			`spirit:library="Testbench"`
339			`spirit:name="toolflow"`
340			`spirit:version="documentation"/>`
341
342			`:Documentation:`
343			`Verilog`
344
345
346
347
348
349
350
351
352
353
354
355
356
357			`enable`
358			`wire`
359			`in`
360
361
362
363
364			`rcv_data_avail`
365			`wire`
366			`out`
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381			`mb`
382			`8`
383
384			`mb`
385			`0x00`
386
387
388			`mb_microbus`
389			`0x10`
390			`8`
391
392
393
394			`ps2_data`
395			`0x0`
396			`8`
397			`read-only`
398
399
400
401			`wdata_buf`
402			`0x0`
403			`8`
404			`write-only`
405
406
407
408			`status`
409			`0x2`
410			`8`
411			`read-only`
412
413
414
415			`cntrl`
416			`0x4`
417			`8`
418			`read-write`
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433