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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [xml/] [io_ps2_mouse.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_ps2
mouse  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 

 
 
 

 
 
 
 
 
 
 
 

  gen_registers
  103.0
  none
  common
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  verilog_maker
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.mouse
    
    
      dest_dir
      ../verilog
    
  

 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body.mouse
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.mouse
        verilogSourcemodule
      
 
      
        micro_reg
        ../verilog/io_ps2_mouse_micro_reg
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
 
    
      fs-syn
 
 
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.mouse
        verilogSourcemodule
      
 
      
        micro_reg
        ../verilog/io_ps2_mouse_micro_reg
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
  
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_ps2"
                                   spirit:version="mouse.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
 
enable
wire
in

 
 
 
rcv_data_avail
wire
out

 
y_pos
reg
out
90

 
x_pos
reg
out
90

 
new_packet
reg
out

 
ms_mid
reg
out

 
ms_right
reg
out

 
ms_left
reg
out

 

 

 
 
 


 mb
8

 micro_reg
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   ps2_data
   0x0
   8
   read-only
  
 
 
 
   wdata_buf
   0x0
   8
   write-only
  
 
 
 
   status
   0x2
   8
   read-only
  
 
 
   cntrl
   0x4
   8
   read-write
  
 
 
 
   x_pos
   0x6
   8
   read-only
  
 
 
   y_pos
   0x8
   8
   read-only
  
 
 
  
 
 

 

 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [xml/] [io_ps2_mouse.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_ps2`
40			`mouse default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71			`mb`
72
73
74			`little`
75			`8`
76
77
78
79			`rdata`
80
81			`rdata`
82			`wire`
83			`70`
84
85
86
87
88			`addr`
89
90			`addr`
91			`30`
92
93
94
95
96
97			`wdata`
98
99			`wdata`
100			`70`
101
102
103
104
105
106			`rd`
107
108			`rd`
109
110
111
112
113			`wr`
114
115			`wr`
116
117
118
119
120			`cs`
121
122			`cs`
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144			`gen_registers`
145			`103.0`
146			`none`
147			`common`
148			`./tools/regtool/gen_registers`
149
150
151			`bus_intf`
152			`mb`
153
154
155			`dest_dir`
156			`../verilog`
157
158
159
160
161
162
163
164			`verilog_maker`
165			`104.0`
166			`none`
167			`common`
168			`./tools/verilog/gen_verilog`
169
170
171			`destination`
172			`top.mouse`
173
174
175			`dest_dir`
176			`../verilog`
177
178
179
180
181
182
183
184
185
186
187
188
189			`fs-common`
190
191
192
193			`../verilog/top.body.mouse`
194			`verilogSourcefragment`
195
196
197
198
199
200
201			`fs-sim`
202
203
204
205
206			`../verilog/copyright.v`
207			`verilogSourceinclude`
208
209
210
211
212			`../verilog/common/top.mouse`
213			`verilogSourcemodule`
214
215
216
217			`micro_reg`
218			`../verilog/io_ps2_mouse_micro_reg`
219			`verilogSourcemodule`
220
221
222
223
224
225
226
227
228
229
230
231			`fs-syn`
232
233
234
235
236
237			`../verilog/copyright.v`
238			`verilogSourceinclude`
239
240
241
242
243			`../verilog/common/top.mouse`
244			`verilogSourcemodule`
245
246
247
248			`micro_reg`
249			`../verilog/io_ps2_mouse_micro_reg`
250			`verilogSourcemodule`
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270			`Hierarchical`
271
272
273			`spirit:library="io"`
274			`spirit:name="io_ps2"`
275			`spirit:version="mouse.design"/>`
276
277
278
279			`verilog`
280
281
282			`spirit:library="Testbench"`
283			`spirit:name="toolflow"`
284			`spirit:version="verilog"/>`
285
286
287
288
289
290
291
292
293			`commoncommon`
294			`Verilog`
295
296
297			`fs-common`
298
299
300
301
302			`sim:Simulation:`
303			`Verilog`
304
305
306			`fs-sim`
307
308
309
310
311
312			`syn:Synthesis:`
313			`Verilog`
314
315
316			`fs-syn`
317
318
319
320
321
322			`doc`
323
324
325			`spirit:library="Testbench"`
326			`spirit:name="toolflow"`
327			`spirit:version="documentation"/>`
328
329			`:Documentation:`
330			`Verilog`
331
332
333
334
335
336
337
338
339
340
341
342
343
344			`enable`
345			`wire`
346			`in`
347
348
349
350
351			`rcv_data_avail`
352			`wire`
353			`out`
354
355
356			`y_pos`
357			`reg`
358			`out`
359			`90`
360
361
362			`x_pos`
363			`reg`
364			`out`
365			`90`
366
367
368			`new_packet`
369			`reg`
370			`out`
371
372
373			`ms_mid`
374			`reg`
375			`out`
376
377
378			`ms_right`
379			`reg`
380			`out`
381
382
383			`ms_left`
384			`reg`
385			`out`
386
387
388
389
390
391
392
393
394
395
396			`mb`
397			`8`
398
399			`micro_reg`
400			`0x00`
401
402
403			`mb_microbus`
404			`0x10`
405			`8`
406
407
408
409			`ps2_data`
410			`0x0`
411			`8`
412			`read-only`
413
414
415
416
417			`wdata_buf`
418			`0x0`
419			`8`
420			`write-only`
421
422
423
424
425			`status`
426			`0x2`
427			`8`
428			`read-only`
429
430
431
432			`cntrl`
433			`0x4`
434			`8`
435			`read-write`
436
437
438
439
440			`x_pos`
441			`0x6`
442			`8`
443			`read-only`
444
445
446
447			`y_pos`
448			`0x8`
449			`8`
450			`read-only`
451
452
453
454
455
456
457
458
459
460
461
462
463