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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [xml/] [io_ps2_mouse.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_ps2
mouse  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 

 
 
 

 
 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 
 

  gen_registers
  102.1
  none
  common
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  verilog_maker
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.mouse
    
    
      dest_dir
      ../verilog
    
  

 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body.mouse
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.mouse
        verilogSourcemodule
      
 
      
        micro_reg
        ../verilog/io_ps2_mouse_micro_reg
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
 
    
      fs-syn
 
 
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.mouse
        verilogSourcemodule
      
 
      
        micro_reg
        ../verilog/io_ps2_mouse_micro_reg
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
  
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_ps2"
                                   spirit:version="mouse.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
 
enable
wire
in

 
 
 
rcv_data_avail
wire
out

 
y_pos
reg
out
90

 
x_pos
reg
out
90

 
new_packet
reg
out

 
ms_mid
reg
out

 
ms_right
reg
out

 
ms_left
reg
out

 

 

 
 
 


 mb
8

 micro_reg
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   ps2_data
   0x0
   8
   read-only
  
 
 
 
   wdata_buf
   0x0
   8
   write-only
  
 
 
 
   status
   0x2
   8
   read-only
  
 
 
   cntrl
   0x4
   8
   read-write
  
 
 
 
   x_pos
   0x6
   8
   read-only
  
 
 
   y_pos
   0x8
   8
   read-only
  
 
 
  
 
 

 

 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [xml/] [io_ps2_mouse.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_ps2`
40			`mouse default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71			`mb`
72
73
74			`little`
75			`8`
76
77
78
79			`rdata`
80
81			`rdata`
82			`wire`
83			`70`
84
85
86
87
88			`addr`
89
90			`addr`
91			`30`
92
93
94
95
96
97			`wdata`
98
99			`wdata`
100			`70`
101
102
103
104
105
106			`rd`
107
108			`rd`
109
110
111
112
113			`wr`
114
115			`wr`
116
117
118
119
120			`cs`
121
122			`cs`
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139	133	jt_eaton
140			`elab_verilog`
141			`102.1`
142			`none`
143			`:Simulation:`
144			`./tools/verilog/elab_verilog`
145
146
147			`dest_dir`
148			`io_ports`
149
150
151
152	131	jt_eaton
153
154
155
156	133	jt_eaton
157
158	131	jt_eaton
159			`gen_registers`
160	133	jt_eaton	`102.1`
161	131	jt_eaton	`none`
162			`common`
163			`./tools/regtool/gen_registers`
164
165
166			`bus_intf`
167			`mb`
168
169
170			`dest_dir`
171			`../verilog`
172
173
174
175
176
177
178
179			`verilog_maker`
180			`104.0`
181			`none`
182			`common`
183			`./tools/verilog/gen_verilog`
184
185
186			`destination`
187			`top.mouse`
188
189
190			`dest_dir`
191			`../verilog`
192
193
194
195
196
197
198
199
200
201
202
203
204			`fs-common`
205
206
207
208			`../verilog/top.body.mouse`
209			`verilogSourcefragment`
210
211
212
213
214
215
216			`fs-sim`
217
218
219
220
221			`../verilog/copyright.v`
222			`verilogSourceinclude`
223
224
225
226
227			`../verilog/common/top.mouse`
228			`verilogSourcemodule`
229
230
231
232			`micro_reg`
233			`../verilog/io_ps2_mouse_micro_reg`
234			`verilogSourcemodule`
235
236
237
238
239
240
241
242
243
244
245
246			`fs-syn`
247
248
249
250
251
252			`../verilog/copyright.v`
253			`verilogSourceinclude`
254
255
256
257
258			`../verilog/common/top.mouse`
259			`verilogSourcemodule`
260
261
262
263			`micro_reg`
264			`../verilog/io_ps2_mouse_micro_reg`
265			`verilogSourcemodule`
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285			`Hierarchical`
286
287
288			`spirit:library="io"`
289			`spirit:name="io_ps2"`
290			`spirit:version="mouse.design"/>`
291
292
293
294			`verilog`
295
296
297			`spirit:library="Testbench"`
298			`spirit:name="toolflow"`
299			`spirit:version="verilog"/>`
300
301
302
303
304
305
306
307
308			`commoncommon`
309			`Verilog`
310
311
312			`fs-common`
313
314
315
316
317			`sim:Simulation:`
318			`Verilog`
319
320
321			`fs-sim`
322
323
324
325
326
327			`syn:Synthesis:`
328			`Verilog`
329
330
331			`fs-syn`
332
333
334
335
336
337			`doc`
338
339
340			`spirit:library="Testbench"`
341			`spirit:name="toolflow"`
342			`spirit:version="documentation"/>`
343
344			`:Documentation:`
345			`Verilog`
346
347
348
349
350
351
352
353
354
355
356
357
358
359			`enable`
360			`wire`
361			`in`
362
363
364
365
366			`rcv_data_avail`
367			`wire`
368			`out`
369
370
371			`y_pos`
372			`reg`
373			`out`
374			`90`
375
376
377			`x_pos`
378			`reg`
379			`out`
380			`90`
381
382
383			`new_packet`
384			`reg`
385			`out`
386
387
388			`ms_mid`
389			`reg`
390			`out`
391
392
393			`ms_right`
394			`reg`
395			`out`
396
397
398			`ms_left`
399			`reg`
400			`out`
401
402
403
404
405
406
407
408
409
410
411			`mb`
412			`8`
413
414			`micro_reg`
415			`0x00`
416
417
418			`mb_microbus`
419			`0x10`
420			`8`
421
422
423
424			`ps2_data`
425			`0x0`
426			`8`
427			`read-only`
428
429
430
431
432			`wdata_buf`
433			`0x0`
434			`8`
435			`write-only`
436
437
438
439
440			`status`
441			`0x2`
442			`8`
443			`read-only`
444
445
446
447			`cntrl`
448			`0x4`
449			`8`
450			`read-write`
451
452
453
454
455			`x_pos`
456			`0x6`
457			`8`
458			`read-only`
459
460
461
462			`y_pos`
463			`0x8`
464			`8`
465			`read-only`
466
467
468
469
470
471
472
473
474
475
476
477
478