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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [sim/] [testbenches/] [xml/] [io_ps2_def_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_ps2
def_tb
 
 
 
 
 
 

 
 
 

  elab_verilog
  103.0
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog

 
 

  trace_bus
  103.0
  none
  :*Simulation:*
  ./tools/verilog/trace_bus
    
    
      path
      root.dut
    
    
      bus_name
      mb
    
  
 

 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 
 


    BUS_ADDR_WIDTH4
    addr_width4
    PS2_MODEL_CLKCNT8'h7f
    PS2_MODEL_SIZE8

 
       
 
 
              
              Params
              
              
                                   spirit:library="io"
                                   spirit:name="io_ps2"
                                   spirit:version="def_dut.params"/>
             
              
 
 
 
              
              Bfm
              
                                   spirit:library="io"
                                   spirit:name="io_ps2"
                                   spirit:version="bfm.design"/>
              
 
 
 
 
 
              
              Ps2_bfm
              
              
                                   spirit:library="Testbench"
                                   spirit:name="ps2_model"
                                   spirit:version="bfm"/>
              
              
 
 
 
 
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              headersheaders
                            Verilog
              
              
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 

 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
 
 
 
    
 
 
 
 
 
 
  
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [sim/] [testbenches/] [xml/] [io_ps2_def_tb.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_ps2`
40			`def_tb`
41
42
43
44
45
46
47
48
49
50
51
52			`elab_verilog`
53			`103.0`
54			`none`
55			`:Simulation:`
56			`./tools/verilog/elab_verilog`
57
58
59
60
61			`trace_bus`
62			`103.0`
63			`none`
64			`:Simulation:`
65			`./tools/verilog/trace_bus`
66
67
68			`path`
69			`root.dut`
70
71
72			`bus_name`
73			`mb`
74
75
76
77
78
79
80
81
82
83
84			`gen_verilog`
85			`104.0`
86			`none`
87			`common`
88			`./tools/verilog/gen_verilog`
89
90
91			`destination`
92			`top.tb`
93
94
95			`dest_dir`
96			`../verilog`
97
98
99			`top`
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114			`BUS_ADDR_WIDTH4`
115			`addr_width4`
116			`PS2_MODEL_CLKCNT8'h7f`
117			`PS2_MODEL_SIZE8`
118
119
120
121
122
123
124			`Params`
125
126
127			`spirit:library="io"`
128			`spirit:name="io_ps2"`
129			`spirit:version="def_dut.params"/>`
130
131
132
133
134
135
136			`Bfm`
137
138			`spirit:library="io"`
139			`spirit:name="io_ps2"`
140			`spirit:version="bfm.design"/>`
141
142
143
144
145
146
147
148			`Ps2_bfm`
149
150
151			`spirit:library="Testbench"`
152			`spirit:name="ps2_model"`
153			`spirit:version="bfm"/>`
154
155
156
157
158
159
160
161
162
163
164			`icarus`
165
166
167			`spirit:library="Testbench"`
168			`spirit:name="toolflow"`
169			`spirit:version="icarus"/>`
170
171
172
173
174
175
176
177
178			`headersheaders`
179			`Verilog`
180
181
182
183
184			`commoncommon`
185			`Verilog`
186
187
188			`fs-common`
189
190
191
192
193			`sim:Simulation:`
194			`Verilog`
195
196
197			`fs-sim`
198
199
200
201
202
203
204			`lint:Lint:`
205			`Verilog`
206
207
208			`fs-lint`
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224			`fs-common`
225
226
227
228			`../verilog/tb.ext`
229			`verilogSourcefragment`
230
231
232
233
234
235
236
237			`fs-sim`
238
239
240
241			`../verilog/common/top.tb`
242			`verilogSourcemodule`
243
244
245
246
247
248
249			`fs-lint`
250
251
252
253			`../verilog/common/top.tb`
254			`verilogSourcemodule`
255
256
257
258
259
260
261
262
263
264
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