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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [sim/] [testbenches/] [xml/] [io_ps2_def_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_ps2
def_tb
 
 
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 
 


    BUS_ADDR_WIDTH4
    addr_width4
    PS2_MODEL_CLKCNT8'h7f
    PS2_MODEL_SIZE8

 
       
 
 
              
              Params
              
              
                                   spirit:library="io"
                                   spirit:name="io_ps2"
                                   spirit:version="def_dut.params"/>
             
              
 
 
 
              
              Bfm
              
                                   spirit:library="io"
                                   spirit:name="io_ps2"
                                   spirit:version="bfm.design"/>
              
 
 
 
 
 
              
              Ps2_bfm
              
              
                                   spirit:library="Testbench"
                                   spirit:name="ps2_model"
                                   spirit:version="bfm"/>
              
              
 
 
 
 
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              headersheaders
                            Verilog
              
              
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 

 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
 
 
 
    
 
 
 
 
 
 
  
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [sim/] [testbenches/] [xml/] [io_ps2_def_tb.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_ps2`
40			`def_tb`
41
42
43
44
45
46
47
48
49
50
51
52
53			`gen_verilog`
54			`104.0`
55			`none`
56			`common`
57			`./tools/verilog/gen_verilog`
58
59
60			`destination`
61			`top.tb`
62
63
64			`dest_dir`
65			`../verilog`
66
67
68			`top`
69
70
71
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73
74
75
76
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81
82
83			`BUS_ADDR_WIDTH4`
84			`addr_width4`
85			`PS2_MODEL_CLKCNT8'h7f`
86			`PS2_MODEL_SIZE8`
87
88
89
90
91
92
93			`Params`
94
95
96			`spirit:library="io"`
97			`spirit:name="io_ps2"`
98			`spirit:version="def_dut.params"/>`
99
100
101
102
103
104
105			`Bfm`
106
107			`spirit:library="io"`
108			`spirit:name="io_ps2"`
109			`spirit:version="bfm.design"/>`
110
111
112
113
114
115
116
117			`Ps2_bfm`
118
119
120			`spirit:library="Testbench"`
121			`spirit:name="ps2_model"`
122			`spirit:version="bfm"/>`
123
124
125
126
127
128
129
130
131
132
133			`icarus`
134
135
136			`spirit:library="Testbench"`
137			`spirit:name="toolflow"`
138			`spirit:version="icarus"/>`
139
140
141
142
143
144
145
146
147			`headersheaders`
148			`Verilog`
149
150
151
152
153			`commoncommon`
154			`Verilog`
155
156
157			`fs-common`
158
159
160
161
162			`sim:Simulation:`
163			`Verilog`
164
165
166			`fs-sim`
167
168
169
170
171
172
173			`lint:Lint:`
174			`Verilog`
175
176
177			`fs-lint`
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193			`fs-common`
194
195
196
197			`../verilog/tb.ext`
198			`verilogSourcefragment`
199
200
201
202
203
204
205
206			`fs-sim`
207
208
209
210			`../verilog/common/top.tb`
211			`verilogSourcemodule`
212
213
214
215
216
217
218			`fs-lint`
219
220
221
222			`../verilog/common/top.tb`
223			`verilogSourcemodule`
224
225
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227
228
229
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