URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [sim/] [testbenches/] [xml/] [io_ps2_def_tb.xml] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_ps2
def_tb
 
 
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      io_ps2_def_tb
    
  

 
 
 

 
 
 
 
 


    BUS_ADDR_WIDTH4
    addr_width4
    PS2_MODEL_CLKCNT8'h7f
    PS2_MODEL_SIZE8

 
       
 
 
              
              Params
              
              
                                   spirit:library="io"
                                   spirit:name="io_ps2"
                                   spirit:version="def_dut.params"/>
             
              
 
 
 
              
              Bfm
              
                                   spirit:library="io"
                                   spirit:name="io_ps2"
                                   spirit:version="bfm.design"/>
              
 
 
 
 
 
              
              Ps2_bfm
              
              
                                   spirit:library="Testbench"
                                   spirit:name="ps2_model"
                                   spirit:version="bfm"/>
              
              
 
 
 
 
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              headersheaders
                            Verilog
              
              
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 

 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/common/io_ps2_def_tb
        verilogSourcemodule
      
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/io_ps2_def_tb
        verilogSourcemodule
      
 
 
 
 
 
 
    
 
 
 
 
 
 
  
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [sim/] [testbenches/] [xml/] [io_ps2_def_tb.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_ps2`
40			`def_tb`
41
42
43
44
45
46
47
48
49
50
51
52
53			`gen_verilog`
54			`104.0`
55			`none`
56			`common`
57			`./tools/verilog/gen_verilog`
58
59
60			`destination`
61	134	jt_eaton	`io_ps2_def_tb`
62	131	jt_eaton
63
64
65
66
67
68
69
70
71
72
73
74
75
76			`BUS_ADDR_WIDTH4`
77			`addr_width4`
78			`PS2_MODEL_CLKCNT8'h7f`
79			`PS2_MODEL_SIZE8`
80
81
82
83
84
85
86			`Params`
87
88
89			`spirit:library="io"`
90			`spirit:name="io_ps2"`
91			`spirit:version="def_dut.params"/>`
92
93
94
95
96
97
98			`Bfm`
99
100			`spirit:library="io"`
101			`spirit:name="io_ps2"`
102			`spirit:version="bfm.design"/>`
103
104
105
106
107
108
109
110			`Ps2_bfm`
111
112
113			`spirit:library="Testbench"`
114			`spirit:name="ps2_model"`
115			`spirit:version="bfm"/>`
116
117
118
119
120
121
122
123
124
125
126			`icarus`
127
128
129			`spirit:library="Testbench"`
130			`spirit:name="toolflow"`
131			`spirit:version="icarus"/>`
132
133
134
135
136
137
138
139
140			`headersheaders`
141			`Verilog`
142
143
144
145
146			`commoncommon`
147			`Verilog`
148
149
150			`fs-common`
151
152
153
154
155			`sim:Simulation:`
156			`Verilog`
157
158
159			`fs-sim`
160
161
162
163
164
165
166			`lint:Lint:`
167			`Verilog`
168
169
170			`fs-lint`
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186			`fs-common`
187
188
189
190			`../verilog/tb.ext`
191			`verilogSourcefragment`
192
193
194
195
196
197
198
199			`fs-sim`
200
201
202
203	134	jt_eaton	`../verilog/common/io_ps2_def_tb`
204	131	jt_eaton	`verilogSourcemodule`
205
206
207
208
209
210
211			`fs-lint`
212
213
214
215	134	jt_eaton	`../verilog/common/io_ps2_def_tb`
216	131	jt_eaton	`verilogSourcemodule`
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235