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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [rtl/] [xml/] [io_timer_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_timer
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
mb
   
   
   little
   8
     
 
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 
 

 
 
 

 
 
 
 
 

  gen_registers
  103.0
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

 
 
  
 
 
    
 
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
    
 
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_timer_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_timer"
                                   spirit:version="def.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 

TIMERS2

 

 
 
enable
wire
in

 
 
irq
reg
out
TIMERS-10

 


 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   timer_0_start
   0x0
   8
   read-only
  
 
 
   timer_0_count
   0x2
   8
   read-only
  
 
 
   timer_0_end
   0x4
   8
   write-only
  
 
 
 
   timer_1_start
   0x8
   8
   read-only
  
 
 
   timer_1_count
   0xa
   8
   read-only
  
 
 
   timer_1_end
   0xc
   8
   write-only
  
 
  
 
 

 

 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [rtl/] [xml/] [io_timer_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_timer`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72			`mb`
73
74
75			`little`
76			`8`
77
78
79
80
81			`rdata`
82
83			`rdata`
84			`wire`
85			`70`
86
87
88
89
90			`addr`
91
92			`addr`
93			`30`
94
95
96
97
98
99			`wdata`
100
101			`wdata`
102			`70`
103
104
105
106
107
108			`rd`
109
110			`rd`
111
112
113
114
115			`wr`
116
117			`wr`
118
119
120
121
122			`cs`
123
124			`cs`
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144			`gen_registers`
145			`103.0`
146			`common`
147			`none`
148			`./tools/regtool/gen_registers`
149
150
151			`bus_intf`
152			`mb`
153
154
155			`dest_dir`
156			`../verilog`
157
158
159
160
161
162
163
164			`gen_verilog`
165			`104.0`
166			`none`
167			`common`
168			`./tools/verilog/gen_verilog`
169
170
171			`destination`
172			`top`
173
174
175			`dest_dir`
176			`../verilog`
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192			`fs-common`
193
194
195
196			`../verilog/top.body`
197			`verilogSourcefragment`
198
199
200
201
202
203
204
205
206
207
208			`fs-sim`
209
210
211
212			`../verilog/copyright.v`
213			`verilogSourceinclude`
214
215
216
217
218			`../verilog/common/top`
219			`verilogSourcemodule`
220
221
222
223			`mb`
224			`../verilog/io_timer_def_mb`
225			`verilogSourcemodule`
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247			`Hierarchical`
248
249
250			`spirit:library="io"`
251			`spirit:name="io_timer"`
252			`spirit:version="def.design"/>`
253
254
255
256			`verilog`
257
258
259			`spirit:library="Testbench"`
260			`spirit:name="toolflow"`
261			`spirit:version="verilog"/>`
262
263
264
265
266
267
268
269
270
271			`commoncommon`
272			`Verilog`
273
274
275			`fs-common`
276
277
278
279
280			`sim:Simulation:`
281			`Verilog`
282
283
284			`fs-sim`
285
286
287
288
289			`syn:Synthesis:`
290			`Verilog`
291
292
293			`fs-sim`
294
295
296
297
298
299			`doc`
300
301
302			`spirit:library="Testbench"`
303			`spirit:name="toolflow"`
304			`spirit:version="documentation"/>`
305
306			`:Documentation:`
307			`Verilog`
308
309
310
311
312
313
314
315
316			`TIMERS2`
317
318
319
320
321
322			`enable`
323			`wire`
324			`in`
325
326
327
328			`irq`
329			`reg`
330			`out`
331			`TIMERS-10`
332
333
334
335
336
337
338
339
340
341
342			`mb`
343			`8`
344
345			`mb`
346			`0x00`
347
348
349			`mb_microbus`
350			`0x10`
351			`8`
352
353
354
355			`timer_0_start`
356			`0x0`
357			`8`
358			`read-only`
359
360
361
362			`timer_0_count`
363			`0x2`
364			`8`
365			`read-only`
366
367
368
369			`timer_0_end`
370			`0x4`
371			`8`
372			`write-only`
373
374
375
376
377			`timer_1_start`
378			`0x8`
379			`8`
380			`read-only`
381
382
383
384			`timer_1_count`
385			`0xa`
386			`8`
387			`read-only`
388
389
390
391			`timer_1_end`
392			`0xc`
393			`8`
394			`write-only`
395
396
397
398
399
400
401
402
403
404
405
406