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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [rtl/] [xml/] [io_timer_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_timer
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
mb
   
   
   little
   8
     
 
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 
 

 
 
 

 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

 
 
  
 
 
    
 
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
    
 
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_timer_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 

       
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 

TIMERS2

 

 
 
enable
wire
in

 
 
irq
reg
out
TIMERS-10

 


 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   timer_0_start
   0x0
   8
   read-only
  
 
 
   timer_0_count
   0x2
   8
   read-only
  
 
 
   timer_0_end
   0x4
   8
   write-only
  
 
 
 
   timer_1_start
   0x8
   8
   read-only
  
 
 
   timer_1_count
   0xa
   8
   read-only
  
 
 
   timer_1_end
   0xc
   8
   write-only
  
 
  
 
 

 

 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [rtl/] [xml/] [io_timer_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_timer`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72			`mb`
73
74
75			`little`
76			`8`
77
78
79
80
81			`rdata`
82
83			`rdata`
84			`wire`
85			`70`
86
87
88
89
90			`addr`
91
92			`addr`
93			`30`
94
95
96
97
98
99			`wdata`
100
101			`wdata`
102			`70`
103
104
105
106
107
108			`rd`
109
110			`rd`
111
112
113
114
115			`wr`
116
117			`wr`
118
119
120
121
122			`cs`
123
124			`cs`
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141	133	jt_eaton
142			`elab_verilog`
143			`102.1`
144			`none`
145			`:Simulation:`
146			`./tools/verilog/elab_verilog`
147
148
149			`dest_dir`
150			`io_ports`
151
152
153
154	131	jt_eaton
155
156	133	jt_eaton
157
158
159	131	jt_eaton
160			`gen_registers`
161	133	jt_eaton	`102.1`
162	131	jt_eaton	`common`
163			`none`
164			`./tools/regtool/gen_registers`
165
166
167			`bus_intf`
168			`mb`
169
170
171			`dest_dir`
172			`../verilog`
173
174
175
176
177
178
179
180			`gen_verilog`
181			`104.0`
182			`none`
183			`common`
184			`./tools/verilog/gen_verilog`
185
186
187			`destination`
188			`top`
189
190
191			`dest_dir`
192			`../verilog`
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208			`fs-common`
209
210
211
212			`../verilog/top.body`
213			`verilogSourcefragment`
214
215
216
217
218
219
220
221
222
223
224			`fs-sim`
225
226
227
228			`../verilog/copyright.v`
229			`verilogSourceinclude`
230
231
232
233
234			`../verilog/common/top`
235			`verilogSourcemodule`
236
237
238
239			`mb`
240			`../verilog/io_timer_def_mb`
241			`verilogSourcemodule`
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264			`verilog`
265
266
267			`spirit:library="Testbench"`
268			`spirit:name="toolflow"`
269			`spirit:version="verilog"/>`
270
271
272
273
274
275
276
277
278
279			`commoncommon`
280			`Verilog`
281
282
283			`fs-common`
284
285
286
287
288			`sim:Simulation:`
289			`Verilog`
290
291
292			`fs-sim`
293
294
295
296
297			`syn:Synthesis:`
298			`Verilog`
299
300
301			`fs-sim`
302
303
304
305
306
307			`doc`
308
309
310			`spirit:library="Testbench"`
311			`spirit:name="toolflow"`
312			`spirit:version="documentation"/>`
313
314			`:Documentation:`
315			`Verilog`
316
317
318
319
320
321
322
323
324			`TIMERS2`
325
326
327
328
329
330			`enable`
331			`wire`
332			`in`
333
334
335
336			`irq`
337			`reg`
338			`out`
339			`TIMERS-10`
340
341
342
343
344
345
346
347
348
349
350			`mb`
351			`8`
352
353			`mb`
354			`0x00`
355
356
357			`mb_microbus`
358			`0x10`
359			`8`
360
361
362
363			`timer_0_start`
364			`0x0`
365			`8`
366			`read-only`
367
368
369
370			`timer_0_count`
371			`0x2`
372			`8`
373			`read-only`
374
375
376
377			`timer_0_end`
378			`0x4`
379			`8`
380			`write-only`
381
382
383
384
385			`timer_1_start`
386			`0x8`
387			`8`
388			`read-only`
389
390
391
392			`timer_1_count`
393			`0xa`
394			`8`
395			`read-only`
396
397
398
399			`timer_1_end`
400			`0xc`
401			`8`
402			`write-only`
403
404
405
406
407
408
409
410
411
412
413
414