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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [rtl/] [xml/] [io_timer_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_timer
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
mb
   
   
   little
   8
     
 
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 
 

 
 
 

 
 
 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      io_timer_def
    
  

 
 
 
 

 
 
  
 
 
    
 
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
    
 
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_timer_def
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_timer_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 

       
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 

TIMERS2

 

 
 
enable
wire
in

 
 
irq
reg
out
TIMERS-10

 


 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   timer_0_start
   0x0
   8
   read-only
  
 
 
   timer_0_count
   0x2
   8
   read-only
  
 
 
   timer_0_end
   0x4
   8
   write-only
  
 
 
 
   timer_1_start
   0x8
   8
   read-only
  
 
 
   timer_1_count
   0xa
   8
   read-only
  
 
 
   timer_1_end
   0xc
   8
   write-only
  
 
  
 
 

 

 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [rtl/] [xml/] [io_timer_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_timer`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72			`mb`
73
74
75			`little`
76			`8`
77
78
79
80
81			`rdata`
82
83			`rdata`
84			`wire`
85			`70`
86
87
88
89
90			`addr`
91
92			`addr`
93			`30`
94
95
96
97
98
99			`wdata`
100
101			`wdata`
102			`70`
103
104
105
106
107
108			`rd`
109
110			`rd`
111
112
113
114
115			`wr`
116
117			`wr`
118
119
120
121
122			`cs`
123
124			`cs`
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143	133	jt_eaton
144	131	jt_eaton
145			`gen_registers`
146	133	jt_eaton	`102.1`
147	131	jt_eaton	`common`
148			`none`
149			`./tools/regtool/gen_registers`
150
151
152			`bus_intf`
153			`mb`
154
155
156			`dest_dir`
157			`../verilog`
158
159
160
161
162
163
164
165			`gen_verilog`
166			`104.0`
167			`none`
168			`common`
169			`./tools/verilog/gen_verilog`
170
171
172			`destination`
173	134	jt_eaton	`io_timer_def`
174	131	jt_eaton
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189			`fs-common`
190
191
192
193			`../verilog/top.body`
194			`verilogSourcefragment`
195
196
197
198
199
200
201
202
203
204
205			`fs-sim`
206
207
208
209			`../verilog/copyright.v`
210			`verilogSourceinclude`
211
212
213
214
215	134	jt_eaton	`../verilog/common/io_timer_def`
216	131	jt_eaton	`verilogSourcemodule`
217
218
219
220			`mb`
221			`../verilog/io_timer_def_mb`
222			`verilogSourcemodule`
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245			`verilog`
246
247
248			`spirit:library="Testbench"`
249			`spirit:name="toolflow"`
250			`spirit:version="verilog"/>`
251
252
253
254
255
256
257
258
259
260			`commoncommon`
261			`Verilog`
262
263
264			`fs-common`
265
266
267
268
269			`sim:Simulation:`
270			`Verilog`
271
272
273			`fs-sim`
274
275
276
277
278			`syn:Synthesis:`
279			`Verilog`
280
281
282			`fs-sim`
283
284
285
286
287
288			`doc`
289
290
291			`spirit:library="Testbench"`
292			`spirit:name="toolflow"`
293			`spirit:version="documentation"/>`
294
295			`:Documentation:`
296			`Verilog`
297
298
299
300
301
302
303
304
305			`TIMERS2`
306
307
308
309
310
311			`enable`
312			`wire`
313			`in`
314
315
316
317			`irq`
318			`reg`
319			`out`
320			`TIMERS-10`
321
322
323
324
325
326
327
328
329
330
331			`mb`
332			`8`
333
334			`mb`
335			`0x00`
336
337
338			`mb_microbus`
339			`0x10`
340			`8`
341
342
343
344			`timer_0_start`
345			`0x0`
346			`8`
347			`read-only`
348
349
350
351			`timer_0_count`
352			`0x2`
353			`8`
354			`read-only`
355
356
357
358			`timer_0_end`
359			`0x4`
360			`8`
361			`write-only`
362
363
364
365
366			`timer_1_start`
367			`0x8`
368			`8`
369			`read-only`
370
371
372
373			`timer_1_count`
374			`0xa`
375			`8`
376			`read-only`
377
378
379
380			`timer_1_end`
381			`0xc`
382			`8`
383			`write-only`
384
385
386
387
388
389
390
391
392
393
394
395