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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [sim/] [testbenches/] [xml/] [io_timer_def_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_timer
def_tb
 
 
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      io_timer_def_tb
    
  

 
 

 
 
 
 
 


    BUS_ADDR_WIDTH4

 
 
       
 
              
              Params
              
              
                                   ipxact:library="io"
                                   ipxact:name="io_timer"
                                   ipxact:version="def_dut.params"/>
              
              
 
 
 
              
              Bfm
              
                                   ipxact:library="io"
                                   ipxact:name="io_timer"
                                   ipxact:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
              
              headers
              Verilog
              
              
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 
 

 
 
 
 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.ext
        verilogSourcefragment
      
 
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/common/io_timer_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/io_timer_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_timer`
40			`def_tb`
41	131	jt_eaton
42
43
44
45
46
47	135	jt_eaton
48	131	jt_eaton
49
50
51
52	135	jt_eaton
53			`gen_verilog`
54			`104.0`
55			`none`
56			`:common:`
57			`tools/verilog/gen_verilog`
58
59
60			`destination`
61			`io_timer_def_tb`
62
63
64
65	131	jt_eaton
66
67	135	jt_eaton
68	131	jt_eaton
69
70
71
72
73	135	jt_eaton
74
75			`BUS_ADDR_WIDTH4`
76
77	131	jt_eaton
78
79	135	jt_eaton
80	131	jt_eaton
81	135	jt_eaton
82			`Params`
83
84
85			`ipxact:library="io"`
86			`ipxact:name="io_timer"`
87			`ipxact:version="def_dut.params"/>`
88
89
90	131	jt_eaton
91
92
93	135	jt_eaton
94			`Bfm`
95
96			`ipxact:library="io"`
97			`ipxact:name="io_timer"`
98			`ipxact:version="bfm.design"/>`
99
100	131	jt_eaton
101
102
103	135	jt_eaton
104			`icarus`
105
106
107			`ipxact:library="Testbench"`
108			`ipxact:name="toolflow"`
109			`ipxact:version="icarus"/>`
110
111
112	131	jt_eaton
113	135	jt_eaton
114			`headers`
115			`Verilog`
116
117
118	131	jt_eaton
119
120	135	jt_eaton
121			`common:common:`
122			`Verilog`
123
124
125			`fs-common`
126
127
128	131	jt_eaton
129
130
131	135	jt_eaton
132			`sim:Simulation:`
133			`Verilog`
134
135
136			`fs-sim`
137
138
139	131	jt_eaton
140
141	135	jt_eaton
142			`lint:Lint:`
143			`Verilog`
144
145
146			`fs-lint`
147
148
149	131	jt_eaton
150	135	jt_eaton
151	131	jt_eaton
152
153
154
155
156	135	jt_eaton
157	131	jt_eaton
158
159
160
161
162	135	jt_eaton
163	131	jt_eaton
164
165	135	jt_eaton
166			`fs-common`
167	131	jt_eaton
168	135	jt_eaton
169
170			`../verilog/top.ext`
171			`verilogSourcefragment`
172
173	131	jt_eaton
174
175
176	135	jt_eaton
177	131	jt_eaton
178
179	135	jt_eaton
180			`fs-sim`
181	131	jt_eaton
182	135	jt_eaton
183
184			`../verilog/common/io_timer_def_tb`
185			`verilogSourcemodule`
186
187	131	jt_eaton
188
189
190	135	jt_eaton
191	131	jt_eaton
192
193	135	jt_eaton
194			`fs-lint`
195	131	jt_eaton
196	135	jt_eaton
197
198			`../verilog/common/io_timer_def_tb`
199			`verilogSourcemodule`
200
201	131	jt_eaton
202
203
204	135	jt_eaton
205	131	jt_eaton
206
207
208
209
210	135	jt_eaton
211	131	jt_eaton
212
213
214
215	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [sim/] [testbenches/] [xml/] [io_timer_def_tb.xml] - Blame information for rev 135