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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [sim/] [testbenches/] [xml/] [io_timer_def_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_timer
def_tb
 
 
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      io_timer_def_tb
    
  

 
 

 
 
 
 
 


    BUS_ADDR_WIDTH4

 
 
       
 
              
              Params
              
              
                                   spirit:library="io"
                                   spirit:name="io_timer"
                                   spirit:version="def_dut.params"/>
              
              
 
 
 
              
              Bfm
              
                                   spirit:library="io"
                                   spirit:name="io_timer"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
              
              headers
              Verilog
              
              
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 
 

 
 
 
 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.ext
        verilogSourcefragment
      
 
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/common/io_timer_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/io_timer_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_timer`
40			`def_tb`
41
42
43
44
45
46
47
48
49
50
51
52
53			`gen_verilog`
54			`104.0`
55			`none`
56			`common`
57			`./tools/verilog/gen_verilog`
58
59
60			`destination`
61	134	jt_eaton	`io_timer_def_tb`
62	131	jt_eaton
63
64
65
66
67
68
69
70
71
72
73
74
75			`BUS_ADDR_WIDTH4`
76
77
78
79
80
81
82			`Params`
83
84
85			`spirit:library="io"`
86			`spirit:name="io_timer"`
87			`spirit:version="def_dut.params"/>`
88
89
90
91
92
93
94			`Bfm`
95
96			`spirit:library="io"`
97			`spirit:name="io_timer"`
98			`spirit:version="bfm.design"/>`
99
100
101
102
103
104			`icarus`
105
106
107			`spirit:library="Testbench"`
108			`spirit:name="toolflow"`
109			`spirit:version="icarus"/>`
110
111
112
113
114			`headers`
115			`Verilog`
116
117
118
119
120
121			`commoncommon`
122			`Verilog`
123
124
125			`fs-common`
126
127
128
129
130
131
132			`sim:Simulation:`
133			`Verilog`
134
135
136			`fs-sim`
137
138
139
140
141
142			`lint:Lint:`
143			`Verilog`
144
145
146			`fs-lint`
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166			`fs-common`
167
168
169
170			`../verilog/top.ext`
171			`verilogSourcefragment`
172
173
174
175
176
177
178
179
180			`fs-sim`
181
182
183
184	134	jt_eaton	`../verilog/common/io_timer_def_tb`
185	131	jt_eaton	`verilogSourcemodule`
186
187
188
189
190
191
192
193
194			`fs-lint`
195
196
197
198	134	jt_eaton	`../verilog/common/io_timer_def_tb`
199	131	jt_eaton	`verilogSourcemodule`
200
201
202
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [sim/] [testbenches/] [xml/] [io_timer_def_tb.xml] - Blame information for rev 134