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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [componentCfg.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
opencores.org
io
io_uart
 
 
2
_
_
_
VARIANT

  
   TestBenches
   sim
   testbenches
   testbench
   version
  
  
   Fpgas
   syn
   ise
   chip
   variant
  

 
 
 
 

 
/doc
 

 

 

default
def
def_lint

 PRESCALE5'b01100
 PRE_SIZE5
 DIV0


 
 

rx
rx
rx_lint

 PRESCALE5'b01100
 PRE_SIZE5
 DIV0
 RX_FIFO_SIZE3
 RX_FIFO_WORDS8


 
 
 

tx
tx
tx_lint

 PRESCALE5'b01100
 PRE_SIZE5
 DIV0
 TX_FIFO_SIZE3
 TX_FIFO_WORDS8


 
 
 

rxtx
rxtx
rxtx_lint

 PRESCALE5'b01100
 PRE_SIZE5
 DIV0
 RX_FIFO_SIZE3
 RX_FIFO_WORDS8
 TX_FIFO_SIZE3
 TX_FIFO_WORDS8


 
 
 
 
 
 
 
 
 
 
 
 
 
 

 
 
 

 
 
io_uart/sim
 
 
 
 

 
 

io_uart_def_lint
def_lint

  rtl_check


 
 

io_uart
io_uart_rx_lint
rx_lint

  rtl_check


 
 

io_uart
io_uart_tx_lint
tx_lint

  rtl_check


 
 

io_uart
io_uart_rxtx_lint
rxtx_lint

  rtl_check


 
 
 
 

 
 
 
 
 

 

default
io_uart_def_lint

 
 
 

rx_default
io_uart_rx_lint

 
 

tx_default
io_uart_tx_lint

 
 
 

rxtx_default
io_uart_rxtx_lint

 
 
 
 

 
 
 
 
 

 
 
 

 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [componentCfg.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6	135	jt_eaton	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`opencores.org`
11			`io`
12			`io_uart`
13
14
15			`2`
16			`_`
17			`_`
18			`_`
19			`VARIANT`
20	135	jt_eaton
21
22			`TestBenches`
23			`sim`
24			`testbenches`
25			`testbench`
26			`version`
27
28
29			`Fpgas`
30			`syn`
31			`ise`
32			`chip`
33			`variant`
34
35
36	131	jt_eaton
37
38	135	jt_eaton
39
40	131	jt_eaton
41
42			`/doc`
43
44
45
46	134	jt_eaton
47	131	jt_eaton
48	134	jt_eaton
49			`default`
50			`def`
51			`def_lint`
52
53			`PRESCALE5'b01100`
54			`PRE_SIZE5`
55			`DIV0`
56
57
58	131	jt_eaton
59
60	134	jt_eaton
61			`rx`
62			`rx`
63			`rx_lint`
64
65			`PRESCALE5'b01100`
66			`PRE_SIZE5`
67			`DIV0`
68			`RX_FIFO_SIZE3`
69			`RX_FIFO_WORDS8`
70
71
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73
74
75
76			`tx`
77			`tx`
78			`tx_lint`
79
80			`PRESCALE5'b01100`
81			`PRE_SIZE5`
82			`DIV0`
83			`TX_FIFO_SIZE3`
84			`TX_FIFO_WORDS8`
85
86
87
88
89
90
91			`rxtx`
92			`rxtx`
93			`rxtx_lint`
94
95			`PRESCALE5'b01100`
96			`PRE_SIZE5`
97			`DIV0`
98			`RX_FIFO_SIZE3`
99			`RX_FIFO_WORDS8`
100			`TX_FIFO_SIZE3`
101			`TX_FIFO_WORDS8`
102
103
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105
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122	131	jt_eaton
123
124
125			`io_uart/sim`
126
127
128
129
130
131
132
133
134			`io_uart_def_lint`
135			`def_lint`
136
137			`rtl_check`
138
139
140
141
142
143			`io_uart`
144			`io_uart_rx_lint`
145			`rx_lint`
146
147			`rtl_check`
148
149
150
151
152
153			`io_uart`
154			`io_uart_tx_lint`
155			`tx_lint`
156
157			`rtl_check`
158
159
160
161
162
163			`io_uart`
164			`io_uart_rxtx_lint`
165			`rxtx_lint`
166
167			`rtl_check`
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169
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180
181
182
183			`default`
184			`io_uart_def_lint`
185
186
187
188
189
190			`rx_default`
191			`io_uart_rx_lint`
192
193
194
195
196			`tx_default`
197			`io_uart_tx_lint`
198
199
200
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202
203			`rxtx_default`
204			`io_uart_rxtx_lint`
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