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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_uart
def
 
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
      
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
        
      
  
 
 
 
 
mb
   
  
      
   
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
 
        
      
 
   little
   8
     
 
  
 
 
 

 
 
 

 
 
 
 
 
 

  gen_registers
  102.1
  :*common:*
  none
  tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      io_uart_def
    
  

 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/io_uart_def
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_uart_def_mb
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
 
  
 
 
 
 
  
 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
 
       
 
              
              Hierarchical
               Hierarchical
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 

 
 
enable
wire
in

 
 
 
clk
wire
in

 
 
reset
wire
in

 
 
cs
wire
in

 
 
rd
wire
in

 
wr
wire
in

 
 
addr
wire
in
30

 
 
wdata
wire
in
70

 
 
rdata
wire
out
70

 
 
 
 
 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
reg
out

 
tx_irq
reg
out

 

 

 
 
 
 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   xmit_data
   0x0
   8
   write-only
  
 
 
   rcv_data
   0x2
   8
   read-only
  
 
 
 
   cntrl
   0x4
   8
   read-write
  
 
 
   status
   0x6
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_uart`
40			`def`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46	135	jt_eaton	`slave_clk`
47
48
49
50
51
52
53			`clk`
54			`clk`
55
56
57
58
59
60
61	131	jt_eaton
62
63	135	jt_eaton	`slave_reset`
64
65
66
67
68
69
70			`reset`
71			`reset`
72
73
74
75
76
77
78	131	jt_eaton
79
80
81	135	jt_eaton	`mb`
82
83
84
85
86
87
88			`rdata`
89
90			`rdata`
91			`wire`
92			`70`
93
94
95	131	jt_eaton
96	135	jt_eaton
97			`addr`
98
99			`addr`
100			`30`
101
102
103	131	jt_eaton
104	135	jt_eaton
105			`wdata`
106
107			`wdata`
108			`70`
109
110
111	131	jt_eaton
112
113	135	jt_eaton
114			`rd`
115
116			`rd`
117
118
119	131	jt_eaton
120	135	jt_eaton
121			`wr`
122
123			`wr`
124
125
126	131	jt_eaton
127	135	jt_eaton
128			`cs`
129
130			`cs`
131
132
133	131	jt_eaton
134	135	jt_eaton
135	131	jt_eaton
136	135	jt_eaton
137
138	131	jt_eaton
139	135	jt_eaton	`little`
140			`8`
141
142	131	jt_eaton
143	135	jt_eaton
144	131	jt_eaton
145
146
147	135	jt_eaton
148	131	jt_eaton
149
150
151	135	jt_eaton
152	131	jt_eaton
153
154
155
156
157
158	135	jt_eaton
159			`gen_registers`
160			`102.1`
161			`:common:`
162			`none`
163			`tools/regtool/gen_registers`
164
165
166			`bus_intf`
167			`mb`
168
169
170			`dest_dir`
171			`../verilog`
172
173
174
175	131	jt_eaton
176	135	jt_eaton
177			`gen_verilog`
178			`104.0`
179			`none`
180			`:common:`
181			`tools/verilog/gen_verilog`
182
183
184			`destination`
185			`io_uart_def`
186
187
188
189	131	jt_eaton
190
191
192
193	135	jt_eaton
194	131	jt_eaton
195
196
197	135	jt_eaton
198	131	jt_eaton
199	135	jt_eaton
200			`fs-common`
201	131	jt_eaton
202	135	jt_eaton
203
204			`../verilog/top.body`
205			`verilogSourcefragment`
206
207	131	jt_eaton
208	135	jt_eaton
209	131	jt_eaton
210	135	jt_eaton
211			`fs-sim`
212	131	jt_eaton
213	135	jt_eaton
214
215			`../verilog/copyright.v`
216			`verilogSourceinclude`
217
218	131	jt_eaton
219
220	135	jt_eaton
221
222			`../verilog/common/io_uart_def`
223			`verilogSourcemodule`
224
225	131	jt_eaton
226	135	jt_eaton
227			`mb`
228			`../verilog/io_uart_def_mb`
229			`verilogSourcemodule`
230
231	131	jt_eaton
232
233
234
235	135	jt_eaton
236	131	jt_eaton
237
238
239
240	135	jt_eaton
241	131	jt_eaton
242
243
244
245	135	jt_eaton
246	131	jt_eaton
247
248	135	jt_eaton
249
250			`Hierarchical`
251
252
253
254	131	jt_eaton
255
256
257	135	jt_eaton
258
259	131	jt_eaton
260	135	jt_eaton
261			`Hierarchical`
262			`Hierarchical`
263
264	131	jt_eaton
265
266	135	jt_eaton
267			`verilog`
268
269
270			`ipxact:library="Testbench"`
271			`ipxact:name="toolflow"`
272			`ipxact:version="verilog"/>`
273
274
275	131	jt_eaton
276
277
278
279
280	135	jt_eaton
281			`common:common:`
282			`Verilog`
283
284
285			`fs-common`
286
287
288	131	jt_eaton
289	135	jt_eaton
290			`sim:Simulation:`
291			`Verilog`
292
293
294			`fs-sim`
295
296
297	131	jt_eaton
298
299	135	jt_eaton
300			`syn:Synthesis:`
301			`Verilog`
302
303
304			`fs-sim`
305
306
307	131	jt_eaton
308
309	135	jt_eaton
310			`doc`
311
312
313			`ipxact:library="Testbench"`
314			`ipxact:name="toolflow"`
315			`ipxact:version="documentation"/>`
316
317			`:Documentation:`
318			`Verilog`
319
320	131	jt_eaton
321
322
323	135	jt_eaton
324	131	jt_eaton
325
326
327
328
329
330
331	135	jt_eaton
332	131	jt_eaton
333
334	135	jt_eaton	`enable`
335			`wire`
336			`in`
337
338	131	jt_eaton
339
340	135	jt_eaton
341			`clk`
342			`wire`
343			`in`
344
345	131	jt_eaton
346
347	135	jt_eaton	`reset`
348			`wire`
349			`in`
350
351	131	jt_eaton
352
353	135	jt_eaton	`cs`
354			`wire`
355			`in`
356
357	131	jt_eaton
358
359	135	jt_eaton	`rd`
360			`wire`
361			`in`
362
363
364			`wr`
365			`wire`
366			`in`
367
368
369
370			`addr`
371			`wire`
372			`in`
373			`30`
374
375
376
377			`wdata`
378			`wire`
379			`in`
380			`70`
381
382
383
384			`rdata`
385			`wire`
386			`out`
387			`70`
388
389
390
391
392
393
394
395			`cts_pad_in`
396			`wire`
397			`in`
398
399
400			`rts_pad_out`
401			`wire`
402			`out`
403
404
405			`rx_irq`
406			`reg`
407			`out`
408
409
410			`tx_irq`
411			`reg`
412			`out`
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427			`mb`
428			`8`
429
430			`mb`
431			`0x00`
432	131	jt_eaton
433	135	jt_eaton
434			`mb_microbus`
435			`0x10`
436			`8`
437	131	jt_eaton
438
439	135	jt_eaton
440			`xmit_data`
441			`0x0`
442			`8`
443			`write-only`
444
445	131	jt_eaton
446	135	jt_eaton
447			`rcv_data`
448			`0x2`
449			`8`
450			`read-only`
451
452	131	jt_eaton
453
454	135	jt_eaton
455			`cntrl`
456			`0x4`
457			`8`
458			`read-write`
459
460	131	jt_eaton
461	135	jt_eaton
462			`status`
463			`0x6`
464			`8`
465			`read-only`
466
467	131	jt_eaton
468
469	135	jt_eaton
470	131	jt_eaton
471
472	135	jt_eaton
473	131	jt_eaton
474	135	jt_eaton
475	131	jt_eaton
476
477
478
479	135	jt_eaton