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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_uart
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 
 

 
 
 

 
 
 
 
 
 

  gen_registers
  103.0
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_uart_def_mb
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
 
  
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_uart"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
PRESCALE5'b01100
PRE_SIZE5
DIV0

 
 

 
 
enable
wire
in

 
 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
reg
out

 
tx_irq
reg
out

 

 

 
 
 
 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   xmit_data
   0x0
   8
   write-only
  
 
 
   rcv_data
   0x2
   8
   read-only
  
 
 
 
   cntrl
   0x4
   8
   read-write
  
 
 
   status
   0x6
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_uart`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72
73			`mb`
74
75
76			`little`
77			`8`
78
79
80
81			`rdata`
82
83			`rdata`
84			`wire`
85			`70`
86
87
88
89
90			`addr`
91
92			`addr`
93			`30`
94
95
96
97
98			`wdata`
99
100			`wdata`
101			`70`
102
103
104
105
106
107			`rd`
108
109			`rd`
110
111
112
113
114			`wr`
115
116			`wr`
117
118
119
120
121			`cs`
122
123			`cs`
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144			`gen_registers`
145			`103.0`
146			`common`
147			`none`
148			`./tools/regtool/gen_registers`
149
150
151			`bus_intf`
152			`mb`
153
154
155			`dest_dir`
156			`../verilog`
157
158
159
160
161
162			`gen_verilog`
163			`104.0`
164			`none`
165			`common`
166			`./tools/verilog/gen_verilog`
167
168
169			`destination`
170			`top`
171
172
173			`dest_dir`
174			`../verilog`
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189			`fs-common`
190
191
192
193			`../verilog/top.body`
194			`verilogSourcefragment`
195
196
197
198
199
200			`fs-sim`
201
202
203
204			`../verilog/copyright.v`
205			`verilogSourceinclude`
206
207
208
209
210
211			`../verilog/common/top`
212			`verilogSourcemodule`
213
214
215
216			`mb`
217			`../verilog/io_uart_def_mb`
218			`verilogSourcemodule`
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238			`Hierarchical`
239
240
241			`spirit:library="io"`
242			`spirit:name="io_uart"`
243			`spirit:version="def.design"/>`
244
245
246
247
248			`verilog`
249
250
251			`spirit:library="Testbench"`
252			`spirit:name="toolflow"`
253			`spirit:version="verilog"/>`
254
255
256
257
258
259
260
261
262			`commoncommon`
263			`Verilog`
264
265
266			`fs-common`
267
268
269
270
271			`sim:Simulation:`
272			`Verilog`
273
274
275			`fs-sim`
276
277
278
279
280
281			`syn:Synthesis:`
282			`Verilog`
283
284
285			`fs-sim`
286
287
288
289
290
291			`doc`
292
293
294			`spirit:library="Testbench"`
295			`spirit:name="toolflow"`
296			`spirit:version="documentation"/>`
297
298			`:Documentation:`
299			`Verilog`
300
301
302
303
304
305
306
307
308
309
310
311
312			`PRESCALE5'b01100`
313			`PRE_SIZE5`
314			`DIV0`
315
316
317
318
319
320
321			`enable`
322			`wire`
323			`in`
324
325
326
327
328			`cts_pad_in`
329			`wire`
330			`in`
331
332
333			`rts_pad_out`
334			`wire`
335			`out`
336
337
338			`rx_irq`
339			`reg`
340			`out`
341
342
343			`tx_irq`
344			`reg`
345			`out`
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360			`mb`
361			`8`
362
363			`mb`
364			`0x00`
365
366
367			`mb_microbus`
368			`0x10`
369			`8`
370
371
372
373			`xmit_data`
374			`0x0`
375			`8`
376			`write-only`
377
378
379
380			`rcv_data`
381			`0x2`
382			`8`
383			`read-only`
384
385
386
387
388			`cntrl`
389			`0x4`
390			`8`
391			`read-write`
392
393
394
395			`status`
396			`0x6`
397			`8`
398			`read-only`
399
400
401
402
403
404
405
406
407
408
409
410
411
412