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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_rx.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_uart
rx  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 
 

 
 
 

 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
   
    
      destination
      top.rx
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.rx
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_uart_rx_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_uart"
                                   spirit:version="rx.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 
 
 

PRESCALE5'b01100
PRE_SIZE5
DIV0
RX_FIFO_SIZE3
RX_FIFO_WORDS8

 
 

 
 
enable
wire
in

 
 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
reg
out

 
tx_irq
reg
out

 

 

 
 
 
 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   xmit_data
   0x0
   8
   write-only
  
 
 
   rcv_data
   0x2
   8
   read-only
  
 
 
 
   cntrl
   0x4
   8
   read-write
  
 
 
   status
   0x6
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_rx.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_uart`
40			`rx default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72
73			`mb`
74
75
76			`little`
77			`8`
78
79
80
81			`rdata`
82
83			`rdata`
84			`wire`
85			`70`
86
87
88
89
90			`addr`
91
92			`addr`
93			`30`
94
95
96
97
98			`wdata`
99
100			`wdata`
101			`70`
102
103
104
105
106
107			`rd`
108
109			`rd`
110
111
112
113
114			`wr`
115
116			`wr`
117
118
119
120
121			`cs`
122
123			`cs`
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140	133	jt_eaton
141			`elab_verilog`
142			`102.1`
143			`none`
144			`:Simulation:`
145			`./tools/verilog/elab_verilog`
146
147
148			`dest_dir`
149			`io_ports`
150
151
152
153	131	jt_eaton
154
155
156	133	jt_eaton
157
158
159	131	jt_eaton
160			`gen_registers`
161	133	jt_eaton	`102.1`
162	131	jt_eaton	`common`
163			`none`
164			`./tools/regtool/gen_registers`
165
166
167			`bus_intf`
168			`mb`
169
170
171			`dest_dir`
172			`../verilog`
173
174
175
176
177
178			`gen_verilog`
179			`104.0`
180			`none`
181			`common`
182			`./tools/verilog/gen_verilog`
183
184
185			`destination`
186	133	jt_eaton	`top.rx`
187	131	jt_eaton
188
189			`dest_dir`
190			`../verilog`
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205			`fs-common`
206
207
208
209			`../verilog/top.body`
210			`verilogSourcefragment`
211
212
213
214
215
216
217			`fs-sim`
218
219
220
221			`../verilog/copyright.v`
222			`verilogSourceinclude`
223
224
225
226
227	133	jt_eaton	`../verilog/common/top.rx`
228	131	jt_eaton	`verilogSourcemodule`
229
230
231
232			`mb`
233			`../verilog/io_uart_rx_mb`
234			`verilogSourcemodule`
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255			`Hierarchical`
256
257
258			`spirit:library="io"`
259			`spirit:name="io_uart"`
260			`spirit:version="rx.design"/>`
261
262
263
264			`verilog`
265
266
267			`spirit:library="Testbench"`
268			`spirit:name="toolflow"`
269			`spirit:version="verilog"/>`
270
271
272
273
274
275
276
277
278			`commoncommon`
279			`Verilog`
280
281
282			`fs-common`
283
284
285
286
287			`sim:Simulation:`
288			`Verilog`
289
290
291			`fs-sim`
292
293
294
295
296			`syn:Synthesis:`
297			`Verilog`
298
299
300			`fs-sim`
301
302
303
304
305
306
307			`doc`
308
309
310			`spirit:library="Testbench"`
311			`spirit:name="toolflow"`
312			`spirit:version="documentation"/>`
313
314			`:Documentation:`
315			`Verilog`
316
317
318
319
320
321
322
323
324
325
326
327
328			`PRESCALE5'b01100`
329			`PRE_SIZE5`
330			`DIV0`
331			`RX_FIFO_SIZE3`
332			`RX_FIFO_WORDS8`
333
334
335
336
337
338
339			`enable`
340			`wire`
341			`in`
342
343
344
345
346			`cts_pad_in`
347			`wire`
348			`in`
349
350
351			`rts_pad_out`
352			`wire`
353			`out`
354
355
356			`rx_irq`
357			`reg`
358			`out`
359
360
361			`tx_irq`
362			`reg`
363			`out`
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378			`mb`
379			`8`
380
381			`mb`
382			`0x00`
383
384
385			`mb_microbus`
386			`0x10`
387			`8`
388
389
390
391			`xmit_data`
392			`0x0`
393			`8`
394			`write-only`
395
396
397
398			`rcv_data`
399			`0x2`
400			`8`
401			`read-only`
402
403
404
405
406			`cntrl`
407			`0x4`
408			`8`
409			`read-write`
410
411
412
413			`status`
414			`0x6`
415			`8`
416			`read-only`
417
418
419
420
421
422
423
424
425
426
427
428
429
430