URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_tx.xml] - Blame information for rev 133

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_uart
tx  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 
 

 
 
 

 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.tx
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.tx
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_uart_tx_mb
        verilogSourcemodule
      
 
    
 
 
 
 
  
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_uart"
                                   spirit:version="tx.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

PRESCALE5'b01100
PRE_SIZE5
DIV0
TX_FIFO_SIZE3
TX_FIFO_WORDS8

 
 

 
 
enable
wire
in

 
 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
reg
out

 
tx_irq
reg
out

 

 

 
 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   xmit_data
   0x0
   8
   write-only
  
 
 
   rcv_data
   0x2
   8
   read-only
  
 
 
 
   cntrl
   0x4
   8
   read-write
  
 
 
   status
   0x6
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_tx.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_uart`
40			`tx default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72
73			`mb`
74
75
76			`little`
77			`8`
78
79
80
81			`rdata`
82
83			`rdata`
84			`wire`
85			`70`
86
87
88
89
90			`addr`
91
92			`addr`
93			`30`
94
95
96
97
98			`wdata`
99
100			`wdata`
101			`70`
102
103
104
105
106
107			`rd`
108
109			`rd`
110
111
112
113
114			`wr`
115
116			`wr`
117
118
119
120
121			`cs`
122
123			`cs`
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140	133	jt_eaton
141			`elab_verilog`
142			`102.1`
143			`none`
144			`:Simulation:`
145			`./tools/verilog/elab_verilog`
146
147
148			`dest_dir`
149			`io_ports`
150
151
152
153	131	jt_eaton
154
155
156	133	jt_eaton
157
158	131	jt_eaton
159			`gen_registers`
160	133	jt_eaton	`102.1`
161	131	jt_eaton	`common`
162			`none`
163			`./tools/regtool/gen_registers`
164
165
166			`bus_intf`
167			`mb`
168
169
170			`dest_dir`
171			`../verilog`
172
173
174
175
176
177			`gen_verilog`
178			`104.0`
179			`none`
180			`common`
181			`./tools/verilog/gen_verilog`
182
183
184			`destination`
185	133	jt_eaton	`top.tx`
186	131	jt_eaton
187
188			`dest_dir`
189			`../verilog`
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204			`fs-common`
205
206
207
208			`../verilog/top.body`
209			`verilogSourcefragment`
210
211
212
213
214
215
216			`fs-sim`
217
218
219
220			`../verilog/copyright.v`
221			`verilogSourceinclude`
222
223
224
225
226	133	jt_eaton	`../verilog/common/top.tx`
227	131	jt_eaton	`verilogSourcemodule`
228
229
230
231			`mb`
232			`../verilog/io_uart_tx_mb`
233			`verilogSourcemodule`
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250			`Hierarchical`
251
252
253			`spirit:library="io"`
254			`spirit:name="io_uart"`
255			`spirit:version="tx.design"/>`
256
257
258
259
260			`verilog`
261
262
263			`spirit:library="Testbench"`
264			`spirit:name="toolflow"`
265			`spirit:version="verilog"/>`
266
267
268
269
270
271
272
273
274			`commoncommon`
275			`Verilog`
276
277
278			`fs-common`
279
280
281
282
283			`sim:Simulation:`
284			`Verilog`
285
286
287			`fs-sim`
288
289
290
291
292
293			`syn:Synthesis:`
294			`Verilog`
295
296
297			`fs-sim`
298
299
300
301
302
303
304			`doc`
305
306
307			`spirit:library="Testbench"`
308			`spirit:name="toolflow"`
309			`spirit:version="documentation"/>`
310
311			`:Documentation:`
312			`Verilog`
313
314
315
316
317
318
319
320
321
322
323
324			`PRESCALE5'b01100`
325			`PRE_SIZE5`
326			`DIV0`
327			`TX_FIFO_SIZE3`
328			`TX_FIFO_WORDS8`
329
330
331
332
333
334
335			`enable`
336			`wire`
337			`in`
338
339
340
341
342			`cts_pad_in`
343			`wire`
344			`in`
345
346
347			`rts_pad_out`
348			`wire`
349			`out`
350
351
352			`rx_irq`
353			`reg`
354			`out`
355
356
357			`tx_irq`
358			`reg`
359			`out`
360
361
362
363
364
365
366
367
368
369
370
371
372			`mb`
373			`8`
374
375			`mb`
376			`0x00`
377
378
379			`mb_microbus`
380			`0x10`
381			`8`
382
383
384
385			`xmit_data`
386			`0x0`
387			`8`
388			`write-only`
389
390
391
392			`rcv_data`
393			`0x2`
394			`8`
395			`read-only`
396
397
398
399
400			`cntrl`
401			`0x4`
402			`8`
403			`read-write`
404
405
406
407			`status`
408			`0x6`
409			`8`
410			`read-only`
411
412
413
414
415
416
417
418
419
420
421
422
423
424