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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_tx.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_uart
tx  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 
 

 
 
 

 
 
 
 
 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      io_uart_tx
    
  

 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_uart_tx
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_uart_tx_mb
        verilogSourcemodule
      
 
    
 
 
 
 
  
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_uart"
                                   spirit:version="tx.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

PRESCALE5'b01100
PRE_SIZE5
DIV0
TX_FIFO_SIZE3
TX_FIFO_WORDS8

 
 

 
 
enable
wire
in

 
 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
reg
out

 
tx_irq
reg
out

 

 

 
 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   xmit_data
   0x0
   8
   write-only
  
 
 
   rcv_data
   0x2
   8
   read-only
  
 
 
 
   cntrl
   0x4
   8
   read-write
  
 
 
   status
   0x6
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_tx.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_uart`
40			`tx default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72
73			`mb`
74
75
76			`little`
77			`8`
78
79
80
81			`rdata`
82
83			`rdata`
84			`wire`
85			`70`
86
87
88
89
90			`addr`
91
92			`addr`
93			`30`
94
95
96
97
98			`wdata`
99
100			`wdata`
101			`70`
102
103
104
105
106
107			`rd`
108
109			`rd`
110
111
112
113
114			`wr`
115
116			`wr`
117
118
119
120
121			`cs`
122
123			`cs`
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143	133	jt_eaton
144
145	131	jt_eaton
146			`gen_registers`
147	133	jt_eaton	`102.1`
148	131	jt_eaton	`common`
149			`none`
150			`./tools/regtool/gen_registers`
151
152
153			`bus_intf`
154			`mb`
155
156
157			`dest_dir`
158			`../verilog`
159
160
161
162
163
164			`gen_verilog`
165			`104.0`
166			`none`
167			`common`
168			`./tools/verilog/gen_verilog`
169
170
171			`destination`
172	134	jt_eaton	`io_uart_tx`
173	131	jt_eaton
174
175
176
177
178
179
180
181
182
183
184
185
186
187			`fs-common`
188
189
190
191			`../verilog/top.body`
192			`verilogSourcefragment`
193
194
195
196
197
198
199			`fs-sim`
200
201
202
203			`../verilog/copyright.v`
204			`verilogSourceinclude`
205
206
207
208
209	134	jt_eaton	`../verilog/common/io_uart_tx`
210	131	jt_eaton	`verilogSourcemodule`
211
212
213
214			`mb`
215			`../verilog/io_uart_tx_mb`
216			`verilogSourcemodule`
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233			`Hierarchical`
234
235
236			`spirit:library="io"`
237			`spirit:name="io_uart"`
238			`spirit:version="tx.design"/>`
239
240
241
242
243			`verilog`
244
245
246			`spirit:library="Testbench"`
247			`spirit:name="toolflow"`
248			`spirit:version="verilog"/>`
249
250
251
252
253
254
255
256
257			`commoncommon`
258			`Verilog`
259
260
261			`fs-common`
262
263
264
265
266			`sim:Simulation:`
267			`Verilog`
268
269
270			`fs-sim`
271
272
273
274
275
276			`syn:Synthesis:`
277			`Verilog`
278
279
280			`fs-sim`
281
282
283
284
285
286
287			`doc`
288
289
290			`spirit:library="Testbench"`
291			`spirit:name="toolflow"`
292			`spirit:version="documentation"/>`
293
294			`:Documentation:`
295			`Verilog`
296
297
298
299
300
301
302
303
304
305
306
307			`PRESCALE5'b01100`
308			`PRE_SIZE5`
309			`DIV0`
310			`TX_FIFO_SIZE3`
311			`TX_FIFO_WORDS8`
312
313
314
315
316
317
318			`enable`
319			`wire`
320			`in`
321
322
323
324
325			`cts_pad_in`
326			`wire`
327			`in`
328
329
330			`rts_pad_out`
331			`wire`
332			`out`
333
334
335			`rx_irq`
336			`reg`
337			`out`
338
339
340			`tx_irq`
341			`reg`
342			`out`
343
344
345
346
347
348
349
350
351
352
353
354
355			`mb`
356			`8`
357
358			`mb`
359			`0x00`
360
361
362			`mb_microbus`
363			`0x10`
364			`8`
365
366
367
368			`xmit_data`
369			`0x0`
370			`8`
371			`write-only`
372
373
374
375			`rcv_data`
376			`0x2`
377			`8`
378			`read-only`
379
380
381
382
383			`cntrl`
384			`0x4`
385			`8`
386			`read-write`
387
388
389
390			`status`
391			`0x6`
392			`8`
393			`read-only`
394
395
396
397
398
399
400
401
402
403
404
405
406
407