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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [sim/] [testbenches/] [xml/] [io_uart_def_lint.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_uart
def_lint
 
 
 
 
 
 
 
 

 

    BUS_ADDR_WIDTH4
    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
       
 
              
              Dut
              
              
                                   spirit:library="io"
                                   spirit:name="io_uart"
                                   spirit:version="def_dut.params"/>
              
              
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
              
              rtl_check
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="rtl_check"/>
              
              
 
 
 
      
 
 
 
 

 
 
 
 
  
 
 
 
 
 
 
    
      fs-lint
 
      
        
        ../verilog/lint/io_uart_def_lint
        verilogSource
        module
      
 
 
    
 
 
 
 
  
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_uart`
40			`def_lint`
41
42
43
44
45
46
47
48
49
50
51
52			`BUS_ADDR_WIDTH4`
53			`UART_MODEL_CLKCNT4'b1100`
54			`UART_MODEL_SIZE4`
55
56
57
58
59
60
61			`Dut`
62
63
64			`spirit:library="io"`
65			`spirit:name="io_uart"`
66			`spirit:version="def_dut.params"/>`
67
68
69
70
71
72			`lint`
73			`:Lint:`
74			`Verilog`
75			`fs-lint`
76
77
78
79
80			`rtl_check`
81
82
83			`spirit:library="Testbench"`
84			`spirit:name="toolflow"`
85			`spirit:version="rtl_check"/>`
86
87
88
89
90
91
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93
94
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96
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109			`fs-lint`
110
111
112
113			`../verilog/lint/io_uart_def_lint`
114			`verilogSource`
115			`module`
116
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [sim/] [testbenches/] [xml/] [io_uart_def_lint.xml] - Blame information for rev 131