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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [sim/] [testbenches/] [xml/] [io_uart_tx_lint.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_uart
tx_lint
 
 
 

 

  elab_verilog
  102.1
  none
  :*Simulation:*
>
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 

  gen_design
  102.1
  none
  :*Simulation:*
>
  ./tools/verilog/gen_design
    
    
      dest_dir
      io_ports
    
  

 

 
 
 
 


    BUS_ADDR_WIDTH4
    PS2_MODEL_CLKCNT8'h7f
    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
       
 
 
 
              
              Dut
              
              
                                   spirit:library="io"
                                   spirit:name="io_uart"
                                   spirit:version="tx_dut.params"/>
              
              
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
              
              rtl_check
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="rtl_check"/>
              
              
 
      
 
 

 
 
 
 
  
 
 
 
 
    
      fs-lint
 
      
        
        ../verilog/lint/io_uart_tx_lint
        verilogSource
        module
      
 
 
 
 
 
    
 
 
 
  
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_uart`
40			`tx_lint`
41
42
43
44	133	jt_eaton
45	131	jt_eaton
46	133	jt_eaton
47			`elab_verilog`
48			`102.1`
49			`none`
50			`:Simulation:`
51			`>`
52			`./tools/verilog/elab_verilog`
53
54
55			`configuration`
56			`default`
57
58
59			`dest_dir`
60			`io_ports`
61
62
63
64	131	jt_eaton
65	133	jt_eaton
66			`gen_design`
67			`102.1`
68			`none`
69			`:Simulation:`
70			`>`
71			`./tools/verilog/gen_design`
72
73
74			`dest_dir`
75			`io_ports`
76
77
78
79	131	jt_eaton
80	133	jt_eaton
81	131	jt_eaton
82	133	jt_eaton
83
84
85	131	jt_eaton
86
87			`BUS_ADDR_WIDTH4`
88			`PS2_MODEL_CLKCNT8'h7f`
89			`UART_MODEL_CLKCNT4'b1100`
90			`UART_MODEL_SIZE4`
91
92
93
94
95
96
97
98			`Dut`
99
100
101			`spirit:library="io"`
102			`spirit:name="io_uart"`
103			`spirit:version="tx_dut.params"/>`
104
105
106
107
108
109			`lint`
110			`:Lint:`
111			`Verilog`
112			`fs-lint`
113
114
115
116
117			`rtl_check`
118
119
120			`spirit:library="Testbench"`
121			`spirit:name="toolflow"`
122			`spirit:version="rtl_check"/>`
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140			`fs-lint`
141
142
143
144			`../verilog/lint/io_uart_tx_lint`
145			`verilogSource`
146			`module`
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [sim/] [testbenches/] [xml/] [io_uart_tx_lint.xml] - Blame information for rev 133