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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [sim/] [testbenches/] [xml/] [io_uart_tx_lint.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_uart
tx_lint
 
 
 
 
 
 
 


    BUS_ADDR_WIDTH4
    PS2_MODEL_CLKCNT8'h7f
    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
       
 
 
 
              
              Dut
              
              
                                   ipxact:library="io"
                                   ipxact:name="io_uart"
                                   ipxact:version="tx_dut.params"/>
              
              
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
              
              rtl_check
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="rtl_check"/>
              
              
 
      
 
 

 
 
 
 
  
 
 
 
 
    
      fs-lint
 
      
        
        ../verilog/lint/io_uart_tx_lint
        verilogSource
        module
      
 
 
 
 
 
    
 
 
 
  
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_uart`
40			`tx_lint`
41	131	jt_eaton
42
43
44
45
46
47
48	135	jt_eaton
49
50			`BUS_ADDR_WIDTH4`
51			`PS2_MODEL_CLKCNT8'h7f`
52			`UART_MODEL_CLKCNT4'b1100`
53			`UART_MODEL_SIZE4`
54
55	131	jt_eaton
56	135	jt_eaton
57	131	jt_eaton
58
59
60	135	jt_eaton
61			`Dut`
62
63
64			`ipxact:library="io"`
65			`ipxact:name="io_uart"`
66			`ipxact:version="tx_dut.params"/>`
67
68
69	131	jt_eaton
70
71	135	jt_eaton
72			`lint`
73			`:Lint:`
74			`Verilog`
75			`fs-lint`
76
77	131	jt_eaton
78
79	135	jt_eaton
80			`rtl_check`
81
82
83			`ipxact:library="Testbench"`
84			`ipxact:name="toolflow"`
85			`ipxact:version="rtl_check"/>`
86
87
88	131	jt_eaton
89	135	jt_eaton
90	131	jt_eaton
91
92	135	jt_eaton
93	131	jt_eaton
94
95
96
97	135	jt_eaton
98	131	jt_eaton
99
100
101
102	135	jt_eaton
103			`fs-lint`
104	131	jt_eaton
105	135	jt_eaton
106
107			`../verilog/lint/io_uart_tx_lint`
108			`verilogSource`
109			`module`
110
111	131	jt_eaton
112
113
114
115
116	135	jt_eaton
117	131	jt_eaton
118
119
120	135	jt_eaton
121	131	jt_eaton
122
123
124	135	jt_eaton

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [sim/] [testbenches/] [xml/] [io_uart_tx_lint.xml] - Blame information for rev 135