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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_utimer/] [rtl/] [verilog/] [top.body] - Blame information for rev 131

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parameter TIMER_LATCH  = 4'h0;
parameter TIMER_COUNT  = 4'h2;
 
 
wire [7:0]              count;
reg  [7:0]              next_count;
wire [7:0]              latch;
 
reg [5:0]              u_sec;
 
 
 
 
 
 
 
always@( posedge clk)
if(reset)                                                                     u_sec <= FREQ-1;
else
if((u_sec == 0) ||   (wr && enable  && cs && addr[3:0] == TIMER_COUNT) )      u_sec <= FREQ-1;
else                                                                          u_sec <= u_sec-1;
 
 
 
always@(*)
if(u_sec == 0)
  begin
  if(count == 8'h00)                                  next_count  = 8'h00;
  else
  if(count == 8'h01)                                  next_count  = latch;
  else                                                next_count  = count-1;
  end
else                                                  next_count  = count;
 
 
 
`VARIANT`MB
utimer_micro_reg
(
      .clk             ( clk        ),
      .reset           ( reset      ),
      .enable          ( enable     ),
 
      .cs              ( cs         ),
      .wr              ( wr         ),
      .rd              ( rd         ),
      .addr            ( addr       ),
      .byte_lanes      ( 1'b1       ),
      .wdata           ( wdata      ),
      .rdata           ( rdata      ),
 
      .latch_cs        (            ),
      .latch_dec       (            ),
      .latch_wr_0      (            ),
      .count_cs        (            ),
      .count_dec       (            ),
      .count_wr_0      (            ),
 
 
      .count           ( count      ),
      .latch           ( latch      ),
 
      .count_rdata     ( count      ),
      .latch_rdata     ( latch      ),
 
      .next_count      ( next_count ),
      .next_latch      ( latch      )
 
);
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2			`parameter TIMER_LATCH = 4'h0;`
3			`parameter TIMER_COUNT = 4'h2;`
4
5
6			`wire [7:0] count;`
7			`reg [7:0] next_count;`
8			`wire [7:0] latch;`
9
10			`reg [5:0] u_sec;`
11
12
13
14
15
16
17
18			`always@( posedge clk)`
19			`if(reset) u_sec <= FREQ-1;`
20			`else`
21			`if((u_sec == 0) \|\| (wr && enable && cs && addr[3:0] == TIMER_COUNT) ) u_sec <= FREQ-1;`
22			`else u_sec <= u_sec-1;`
23
24
25
26			`always@(*)`
27			`if(u_sec == 0)`
28			`begin`
29			`if(count == 8'h00) next_count = 8'h00;`
30			`else`
31			`if(count == 8'h01) next_count = latch;`
32			`else next_count = count-1;`
33			`end`
34			`else next_count = count;`
35
36
37
38			`VARIANT`MB
39			`utimer_micro_reg`
40			`(`
41			`.clk ( clk ),`
42			`.reset ( reset ),`
43			`.enable ( enable ),`
44
45			`.cs ( cs ),`
46			`.wr ( wr ),`
47			`.rd ( rd ),`
48			`.addr ( addr ),`
49			`.byte_lanes ( 1'b1 ),`
50			`.wdata ( wdata ),`
51			`.rdata ( rdata ),`
52
53			`.latch_cs ( ),`
54			`.latch_dec ( ),`
55			`.latch_wr_0 ( ),`
56			`.count_cs ( ),`
57			`.count_dec ( ),`
58			`.count_wr_0 ( ),`
59
60
61			`.count ( count ),`
62			`.latch ( latch ),`
63
64			`.count_rdata ( count ),`
65			`.latch_rdata ( latch ),`
66
67			`.next_count ( next_count ),`
68			`.next_latch ( latch )`
69
70			`);`
71
72
73
74
75
76
77

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_utimer/] [rtl/] [verilog/] [top.body] - Blame information for rev 131