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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_utimer/] [rtl/] [xml/] [io_utimer_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_utimer
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 

 
 
 

 
 
 
 
 
 

  gen_registers
  103.0
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_utimer_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_utimer_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 
 

       
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_utimer"
                                   spirit:version="def.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

FREQ25

 

 
 
enable
wire
in

 
 
 

 

 
 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   latch
   0x0
   8
   read-write
  
 
 
   count
   0x2
   8
   read-write
  
 
 
 
 
  
 
 

 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_utimer/] [rtl/] [xml/] [io_utimer_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_utimer`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72			`mb`
73
74
75			`little`
76			`8`
77
78
79
80			`rdata`
81
82			`rdata`
83			`wire`
84			`70`
85
86
87
88
89			`addr`
90
91			`addr`
92			`30`
93
94
95
96
97			`wdata`
98
99			`wdata`
100			`70`
101
102
103
104
105
106			`rd`
107
108			`rd`
109
110
111
112
113			`wr`
114
115			`wr`
116
117
118
119
120			`cs`
121
122			`cs`
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142			`gen_registers`
143			`103.0`
144			`common`
145			`none`
146			`./tools/regtool/gen_registers`
147
148
149			`bus_intf`
150			`mb`
151
152
153			`dest_dir`
154			`../verilog`
155
156
157
158
159
160			`gen_verilog`
161			`104.0`
162			`none`
163			`common`
164			`./tools/verilog/gen_verilog`
165
166
167			`destination`
168			`top`
169
170
171			`dest_dir`
172			`../verilog`
173
174
175
176
177
178
179
180
181
182
183
184			`fs-common`
185
186
187
188			`../verilog/top.body`
189			`verilogSourcefragment`
190
191
192
193
194
195
196			`fs-sim`
197
198
199
200			`../verilog/copyright.v`
201			`verilogSourceinclude`
202
203
204
205
206			`../verilog/common/top`
207			`verilogSourcemodule`
208
209
210
211			`mb`
212			`../verilog/io_utimer_def_mb`
213			`verilogSourcemodule`
214
215
216
217
218
219
220
221
222
223			`fs-syn`
224
225
226
227			`../verilog/copyright.v`
228			`verilogSourceinclude`
229
230
231
232
233
234			`../verilog/common/top`
235			`verilogSourcemodule`
236
237
238
239			`mb`
240			`../verilog/io_utimer_def_mb`
241			`verilogSourcemodule`
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258			`Hierarchical`
259
260
261			`spirit:library="io"`
262			`spirit:name="io_utimer"`
263			`spirit:version="def.design"/>`
264
265
266
267			`verilog`
268
269
270			`spirit:library="Testbench"`
271			`spirit:name="toolflow"`
272			`spirit:version="verilog"/>`
273
274
275
276
277
278
279
280
281
282			`commoncommon`
283
284			`Verilog`
285
286
287			`fs-common`
288
289
290
291
292			`sim:Simulation:`
293
294			`Verilog`
295
296
297			`fs-sim`
298
299
300
301
302
303			`syn:Synthesis:`
304
305			`Verilog`
306
307
308			`fs-syn`
309
310
311
312
313
314
315			`doc`
316
317
318			`spirit:library="Testbench"`
319			`spirit:name="toolflow"`
320			`spirit:version="documentation"/>`
321
322			`:Documentation:`
323			`Verilog`
324
325
326
327
328
329
330
331
332
333
334			`FREQ25`
335
336
337
338
339
340			`enable`
341			`wire`
342			`in`
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357			`mb`
358			`8`
359
360			`mb`
361			`0x00`
362
363
364			`mb_microbus`
365			`0x10`
366			`8`
367
368
369
370			`latch`
371			`0x0`
372			`8`
373			`read-write`
374
375
376
377			`count`
378			`0x2`
379			`8`
380			`read-write`
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398