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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_utimer/] [rtl/] [xml/] [io_utimer_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_utimer
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 

 
 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_utimer_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_utimer_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 
 

       
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

FREQ25

 

 
 
enable
wire
in

 
 
 

 

 
 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   latch
   0x0
   8
   read-write
  
 
 
   count
   0x2
   8
   read-write
  
 
 
 
 
  
 
 

 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_utimer/] [rtl/] [xml/] [io_utimer_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_utimer`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72			`mb`
73
74
75			`little`
76			`8`
77
78
79
80			`rdata`
81
82			`rdata`
83			`wire`
84			`70`
85
86
87
88
89			`addr`
90
91			`addr`
92			`30`
93
94
95
96
97			`wdata`
98
99			`wdata`
100			`70`
101
102
103
104
105
106			`rd`
107
108			`rd`
109
110
111
112
113			`wr`
114
115			`wr`
116
117
118
119
120			`cs`
121
122			`cs`
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137	133	jt_eaton
138			`elab_verilog`
139			`102.1`
140			`none`
141			`:Simulation:`
142			`./tools/verilog/elab_verilog`
143
144
145			`dest_dir`
146			`io_ports`
147
148
149
150	131	jt_eaton
151
152
153
154	133	jt_eaton
155	131	jt_eaton
156			`gen_registers`
157	133	jt_eaton	`102.1`
158	131	jt_eaton	`common`
159			`none`
160			`./tools/regtool/gen_registers`
161
162
163			`bus_intf`
164			`mb`
165
166
167			`dest_dir`
168			`../verilog`
169
170
171
172
173
174			`gen_verilog`
175			`104.0`
176			`none`
177			`common`
178			`./tools/verilog/gen_verilog`
179
180
181			`destination`
182			`top`
183
184
185			`dest_dir`
186			`../verilog`
187
188
189
190
191
192
193
194
195
196
197
198			`fs-common`
199
200
201
202			`../verilog/top.body`
203			`verilogSourcefragment`
204
205
206
207
208
209
210			`fs-sim`
211
212
213
214			`../verilog/copyright.v`
215			`verilogSourceinclude`
216
217
218
219
220			`../verilog/common/top`
221			`verilogSourcemodule`
222
223
224
225			`mb`
226			`../verilog/io_utimer_def_mb`
227			`verilogSourcemodule`
228
229
230
231
232
233
234
235
236
237			`fs-syn`
238
239
240
241			`../verilog/copyright.v`
242			`verilogSourceinclude`
243
244
245
246
247
248			`../verilog/common/top`
249			`verilogSourcemodule`
250
251
252
253			`mb`
254			`../verilog/io_utimer_def_mb`
255			`verilogSourcemodule`
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273			`verilog`
274
275
276			`spirit:library="Testbench"`
277			`spirit:name="toolflow"`
278			`spirit:version="verilog"/>`
279
280
281
282
283
284
285
286
287
288			`commoncommon`
289
290			`Verilog`
291
292
293			`fs-common`
294
295
296
297
298			`sim:Simulation:`
299
300			`Verilog`
301
302
303			`fs-sim`
304
305
306
307
308
309			`syn:Synthesis:`
310
311			`Verilog`
312
313
314			`fs-syn`
315
316
317
318
319
320
321			`doc`
322
323
324			`spirit:library="Testbench"`
325			`spirit:name="toolflow"`
326			`spirit:version="documentation"/>`
327
328			`:Documentation:`
329			`Verilog`
330
331
332
333
334
335
336
337
338
339
340			`FREQ25`
341
342
343
344
345
346			`enable`
347			`wire`
348			`in`
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363			`mb`
364			`8`
365
366			`mb`
367			`0x00`
368
369
370			`mb_microbus`
371			`0x10`
372			`8`
373
374
375
376			`latch`
377			`0x0`
378			`8`
379			`read-write`
380
381
382
383			`count`
384			`0x2`
385			`8`
386			`read-write`
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404