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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vga/] [rtl/] [verilog/] [top.body] - Blame information for rev 131

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`VARIANT`MB
    #( .CNTRL_RST        (8'b0),
       .CHAR_COLOR_RST   (8'h1c),
       .BACK_COLOR_RST   (8'h01),
       .CURSOR_COLOR_RST (8'he0))
 
 vga_micro_reg
 (
   .clk                ( clk               ),
   .reset              ( reset             ),
   .enable             ( enable            ),
   .cs                 ( cs                ),
   .wr                 ( wr                ),
   .rd                 ( rd                ),
   .byte_lanes         ( 1'b1              ),
   .addr               ( addr              ),
   .wdata              ( wdata             ),
   .rdata              ( rdata             ),
 
 
     .ascii_data_cs        (),
     .ascii_data_dec       (),
     .ascii_data       (),
     .next_ascii_data       (),
     .add_l_cs       (),
     .add_l_dec       (),
     .add_l       (),
     .next_add_l       (),
     .add_h_cs       (),
     .add_h_dec       (),
     .add_h       (),
     .next_add_h       (),
     .vadd_l_cs       (),
     .vadd_l_dec       (),
     .vadd_h_cs       (),
     .vadd_h_dec       (),
     .cntrl_cs       (),
     .cntrl_dec       (),
     .cntrl_wr_0       (),
     .char_color_cs       (),
     .char_color_dec       (),
     .char_color_wr_0       (),
     .back_color_cs       (),
     .back_color_dec       (),
     .back_color_wr_0       (),
     .cursor_color_cs       (),
     .cursor_color_dec       (),
     .cursor_color_wr_0       (),
 
 
 
   .cntrl              ( cntrl             ),
   .char_color         ( char_color        ),
   .back_color         ( back_color        ),
   .cursor_color       ( cursor_color      ),
 
   .next_cntrl         ( cntrl             ),
   .next_char_color    ( char_color        ),
   .next_back_color    ( back_color        ),
   .next_cursor_color  ( cursor_color      ),
 
 
   .cntrl_rdata         ( cntrl             ),
   .char_color_rdata    ( char_color        ),
   .back_color_rdata    ( back_color        ),
   .cursor_color_rdata  ( cursor_color      ),
 
 
 
   .vadd_l_rdata        ( vga_address[7:0]  ),
   .vadd_h_rdata        ( vga_address[15:8] ),
 
   .ascii_data_wr_0     ( ascii_data_wr     ),
   .add_l_wr_0          ( add_l_wr          ),
   .add_h_wr_0          ( add_h_wr          ));
 
 
 
 
always@(posedge clk)
if (reset)     ascii_load          <= 1'b0;
else           ascii_load          <= ascii_data_wr;
 
 
 
 
always@(posedge clk)
if (reset)      add_l_load         <= 1'b0;
else            add_l_load         <= add_l_wr;
 
 
 
 
always@(posedge clk)
if (reset)      add_h_load         <= 1'b0;
else            add_h_load         <= add_h_wr;
 
 
 
 
 
 
 
 
 
 
 
always@(posedge clk)
if (reset)     lat_wdata  <= 8'h00;
else           lat_wdata  <= wdata;

Line No.	Rev	Author	Line
1	131	jt_eaton
2			`VARIANT`MB
3			`#( .CNTRL_RST (8'b0),`
4			`.CHAR_COLOR_RST (8'h1c),`
5			`.BACK_COLOR_RST (8'h01),`
6			`.CURSOR_COLOR_RST (8'he0))`
7
8			`vga_micro_reg`
9			`(`
10			`.clk ( clk ),`
11			`.reset ( reset ),`
12			`.enable ( enable ),`
13			`.cs ( cs ),`
14			`.wr ( wr ),`
15			`.rd ( rd ),`
16			`.byte_lanes ( 1'b1 ),`
17			`.addr ( addr ),`
18			`.wdata ( wdata ),`
19			`.rdata ( rdata ),`
20
21
22			`.ascii_data_cs (),`
23			`.ascii_data_dec (),`
24			`.ascii_data (),`
25			`.next_ascii_data (),`
26			`.add_l_cs (),`
27			`.add_l_dec (),`
28			`.add_l (),`
29			`.next_add_l (),`
30			`.add_h_cs (),`
31			`.add_h_dec (),`
32			`.add_h (),`
33			`.next_add_h (),`
34			`.vadd_l_cs (),`
35			`.vadd_l_dec (),`
36			`.vadd_h_cs (),`
37			`.vadd_h_dec (),`
38			`.cntrl_cs (),`
39			`.cntrl_dec (),`
40			`.cntrl_wr_0 (),`
41			`.char_color_cs (),`
42			`.char_color_dec (),`
43			`.char_color_wr_0 (),`
44			`.back_color_cs (),`
45			`.back_color_dec (),`
46			`.back_color_wr_0 (),`
47			`.cursor_color_cs (),`
48			`.cursor_color_dec (),`
49			`.cursor_color_wr_0 (),`
50
51
52
53			`.cntrl ( cntrl ),`
54			`.char_color ( char_color ),`
55			`.back_color ( back_color ),`
56			`.cursor_color ( cursor_color ),`
57
58			`.next_cntrl ( cntrl ),`
59			`.next_char_color ( char_color ),`
60			`.next_back_color ( back_color ),`
61			`.next_cursor_color ( cursor_color ),`
62
63
64			`.cntrl_rdata ( cntrl ),`
65			`.char_color_rdata ( char_color ),`
66			`.back_color_rdata ( back_color ),`
67			`.cursor_color_rdata ( cursor_color ),`
68
69
70
71			`.vadd_l_rdata ( vga_address[7:0] ),`
72			`.vadd_h_rdata ( vga_address[15:8] ),`
73
74			`.ascii_data_wr_0 ( ascii_data_wr ),`
75			`.add_l_wr_0 ( add_l_wr ),`
76			`.add_h_wr_0 ( add_h_wr ));`
77
78
79
80
81			`always@(posedge clk)`
82			`if (reset) ascii_load <= 1'b0;`
83			`else ascii_load <= ascii_data_wr;`
84
85
86
87
88			`always@(posedge clk)`
89			`if (reset) add_l_load <= 1'b0;`
90			`else add_l_load <= add_l_wr;`
91
92
93
94
95			`always@(posedge clk)`
96			`if (reset) add_h_load <= 1'b0;`
97			`else add_h_load <= add_h_wr;`
98
99
100
101
102
103
104
105
106
107
108
109			`always@(posedge clk)`
110			`if (reset) lat_wdata <= 8'h00;`
111			`else lat_wdata <= wdata;`

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vga/] [rtl/] [verilog/] [top.body] - Blame information for rev 131