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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vga/] [rtl/] [xml/] [io_vga_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_vga
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 

 
 
 
 

 
 
 
 
 
 
 

  gen_registers
  103.0
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_vga_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_vga"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 

 

 

 
enable
wire
in

 
 
 
 
 

 

 
 
 
 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   ascii_data
   0x0
   8
   write-only
  
 
 
   add_l
   0x2
   8
   write-only
  
 
 
   add_h
   0x4
   8
   write-only
  
 
 
 
   vadd_l
   0x2
   8
   read-only
  
 
 
   vadd_h
   0x4
   8
   read-only
  
 
 
 
   cntrl
   0x6
   8
   read-write
  
 
 
 
 
 
   char_color
   0x8
   8
   read-write
  
 
 
 
 
   back_color
   0xa
   8
   read-write
  
 
 
 
   cursor_color
   0xc
   8
   read-write
  
 
  
 
 

 

 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vga/] [rtl/] [xml/] [io_vga_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_vga`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72			`mb`
73
74
75			`little`
76			`8`
77
78
79
80			`rdata`
81
82			`rdata`
83			`wire`
84			`70`
85
86
87
88
89			`addr`
90
91			`addr`
92			`30`
93
94
95
96
97			`wdata`
98
99			`wdata`
100			`70`
101
102
103
104
105
106			`rd`
107
108			`rd`
109
110
111
112
113			`wr`
114
115			`wr`
116
117
118
119
120			`cs`
121
122			`cs`
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144			`gen_registers`
145			`103.0`
146			`common`
147			`none`
148			`./tools/regtool/gen_registers`
149
150
151			`bus_intf`
152			`mb`
153
154
155			`dest_dir`
156			`../verilog`
157
158
159
160
161
162			`gen_verilog`
163			`104.0`
164			`none`
165			`common`
166			`./tools/verilog/gen_verilog`
167
168
169			`destination`
170			`top`
171
172
173			`dest_dir`
174			`../verilog`
175
176
177
178
179
180
181
182
183
184
185
186
187
188			`fs-common`
189
190
191
192			`../verilog/top.body`
193			`verilogSourcefragment`
194
195
196
197
198
199			`fs-sim`
200
201
202
203			`../verilog/copyright.v`
204			`verilogSourceinclude`
205
206
207
208
209
210			`../verilog/common/top`
211			`verilogSourcemodule`
212
213
214
215			`mb`
216			`../verilog/io_vga_def_mb`
217			`verilogSourcemodule`
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236			`Hierarchical`
237
238
239			`spirit:library="io"`
240			`spirit:name="io_vga"`
241			`spirit:version="def.design"/>`
242
243
244
245
246			`verilog`
247
248
249			`spirit:library="Testbench"`
250			`spirit:name="toolflow"`
251			`spirit:version="verilog"/>`
252
253
254
255
256
257
258
259
260			`commoncommon`
261
262			`Verilog`
263
264
265			`fs-common`
266
267
268
269
270			`sim:Simulation:`
271
272			`Verilog`
273
274
275			`fs-sim`
276
277
278
279
280			`syn:Synthesis:`
281
282			`Verilog`
283
284
285			`fs-sim`
286
287
288
289
290
291
292			`doc`
293
294
295			`spirit:library="Testbench"`
296			`spirit:name="toolflow"`
297			`spirit:version="documentation"/>`
298
299			`:Documentation:`
300			`Verilog`
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315			`enable`
316			`wire`
317			`in`
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336			`mb`
337			`8`
338
339			`mb`
340			`0x00`
341
342
343			`mb_microbus`
344			`0x10`
345			`8`
346
347
348
349			`ascii_data`
350			`0x0`
351			`8`
352			`write-only`
353
354
355
356			`add_l`
357			`0x2`
358			`8`
359			`write-only`
360
361
362
363			`add_h`
364			`0x4`
365			`8`
366			`write-only`
367
368
369
370
371			`vadd_l`
372			`0x2`
373			`8`
374			`read-only`
375
376
377
378			`vadd_h`
379			`0x4`
380			`8`
381			`read-only`
382
383
384
385
386			`cntrl`
387			`0x6`
388			`8`
389			`read-write`
390
391
392
393
394
395
396			`char_color`
397			`0x8`
398			`8`
399			`read-write`
400
401
402
403
404
405			`back_color`
406			`0xa`
407			`8`
408			`read-write`
409
410
411
412
413			`cursor_color`
414			`0xc`
415			`8`
416			`read-write`
417
418
419
420
421
422
423
424
425
426
427
428