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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vga/] [rtl/] [xml/] [io_vga_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_vga
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 

 
 
 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_vga_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_vga"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 

 

 

 
enable
wire
in

 
 
 
 
 

 

 
 
 
 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   ascii_data
   0x0
   8
   write-only
  
 
 
   add_l
   0x2
   8
   write-only
  
 
 
   add_h
   0x4
   8
   write-only
  
 
 
 
   vadd_l
   0x2
   8
   read-only
  
 
 
   vadd_h
   0x4
   8
   read-only
  
 
 
 
   cntrl
   0x6
   8
   read-write
  
 
 
 
 
 
   char_color
   0x8
   8
   read-write
  
 
 
 
 
   back_color
   0xa
   8
   read-write
  
 
 
 
   cursor_color
   0xc
   8
   read-write
  
 
  
 
 

 

 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vga/] [rtl/] [xml/] [io_vga_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_vga`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72			`mb`
73
74
75			`little`
76			`8`
77
78
79
80			`rdata`
81
82			`rdata`
83			`wire`
84			`70`
85
86
87
88
89			`addr`
90
91			`addr`
92			`30`
93
94
95
96
97			`wdata`
98
99			`wdata`
100			`70`
101
102
103
104
105
106			`rd`
107
108			`rd`
109
110
111
112
113			`wr`
114
115			`wr`
116
117
118
119
120			`cs`
121
122			`cs`
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138	133	jt_eaton
139			`elab_verilog`
140			`102.1`
141			`none`
142			`:Simulation:`
143			`./tools/verilog/elab_verilog`
144
145
146			`dest_dir`
147			`io_ports`
148
149
150
151	131	jt_eaton
152
153
154
155
156	133	jt_eaton
157	131	jt_eaton
158			`gen_registers`
159	133	jt_eaton	`102.1`
160	131	jt_eaton	`common`
161			`none`
162			`./tools/regtool/gen_registers`
163
164
165			`bus_intf`
166			`mb`
167
168
169			`dest_dir`
170			`../verilog`
171
172
173
174
175
176			`gen_verilog`
177			`104.0`
178			`none`
179			`common`
180			`./tools/verilog/gen_verilog`
181
182
183			`destination`
184			`top`
185
186
187			`dest_dir`
188			`../verilog`
189
190
191
192
193
194
195
196
197
198
199
200
201
202			`fs-common`
203
204
205
206			`../verilog/top.body`
207			`verilogSourcefragment`
208
209
210
211
212
213			`fs-sim`
214
215
216
217			`../verilog/copyright.v`
218			`verilogSourceinclude`
219
220
221
222
223
224			`../verilog/common/top`
225			`verilogSourcemodule`
226
227
228
229			`mb`
230			`../verilog/io_vga_def_mb`
231			`verilogSourcemodule`
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250			`Hierarchical`
251
252
253			`spirit:library="io"`
254			`spirit:name="io_vga"`
255			`spirit:version="def.design"/>`
256
257
258
259
260			`verilog`
261
262
263			`spirit:library="Testbench"`
264			`spirit:name="toolflow"`
265			`spirit:version="verilog"/>`
266
267
268
269
270
271
272
273
274			`commoncommon`
275
276			`Verilog`
277
278
279			`fs-common`
280
281
282
283
284			`sim:Simulation:`
285
286			`Verilog`
287
288
289			`fs-sim`
290
291
292
293
294			`syn:Synthesis:`
295
296			`Verilog`
297
298
299			`fs-sim`
300
301
302
303
304
305
306			`doc`
307
308
309			`spirit:library="Testbench"`
310			`spirit:name="toolflow"`
311			`spirit:version="documentation"/>`
312
313			`:Documentation:`
314			`Verilog`
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329			`enable`
330			`wire`
331			`in`
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350			`mb`
351			`8`
352
353			`mb`
354			`0x00`
355
356
357			`mb_microbus`
358			`0x10`
359			`8`
360
361
362
363			`ascii_data`
364			`0x0`
365			`8`
366			`write-only`
367
368
369
370			`add_l`
371			`0x2`
372			`8`
373			`write-only`
374
375
376
377			`add_h`
378			`0x4`
379			`8`
380			`write-only`
381
382
383
384
385			`vadd_l`
386			`0x2`
387			`8`
388			`read-only`
389
390
391
392			`vadd_h`
393			`0x4`
394			`8`
395			`read-only`
396
397
398
399
400			`cntrl`
401			`0x6`
402			`8`
403			`read-write`
404
405
406
407
408
409
410			`char_color`
411			`0x8`
412			`8`
413			`read-write`
414
415
416
417
418
419			`back_color`
420			`0xa`
421			`8`
422			`read-write`
423
424
425
426
427			`cursor_color`
428			`0xc`
429			`8`
430			`read-write`
431
432
433
434
435
436
437
438
439
440
441
442