URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vga/] [rtl/] [xml/] [io_vga_def.xml] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_vga
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 

 
 
 
 

 
 
 
 
 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      io_vga_def
    
  

 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/io_vga_def
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_vga_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_vga"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 

 

 

 
enable
wire
in

 
 
 
 
 

 

 
 
 
 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   ascii_data
   0x0
   8
   write-only
  
 
 
   add_l
   0x2
   8
   write-only
  
 
 
   add_h
   0x4
   8
   write-only
  
 
 
 
   vadd_l
   0x2
   8
   read-only
  
 
 
   vadd_h
   0x4
   8
   read-only
  
 
 
 
   cntrl
   0x6
   8
   read-write
  
 
 
 
 
 
   char_color
   0x8
   8
   read-write
  
 
 
 
 
   back_color
   0xa
   8
   read-write
  
 
 
 
   cursor_color
   0xc
   8
   read-write
  
 
  
 
 

 

 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vga/] [rtl/] [xml/] [io_vga_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_vga`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72			`mb`
73
74
75			`little`
76			`8`
77
78
79
80			`rdata`
81
82			`rdata`
83			`wire`
84			`70`
85
86
87
88
89			`addr`
90
91			`addr`
92			`30`
93
94
95
96
97			`wdata`
98
99			`wdata`
100			`70`
101
102
103
104
105
106			`rd`
107
108			`rd`
109
110
111
112
113			`wr`
114
115			`wr`
116
117
118
119
120			`cs`
121
122			`cs`
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143	133	jt_eaton
144	131	jt_eaton
145			`gen_registers`
146	133	jt_eaton	`102.1`
147	131	jt_eaton	`common`
148			`none`
149			`./tools/regtool/gen_registers`
150
151
152			`bus_intf`
153			`mb`
154
155
156			`dest_dir`
157			`../verilog`
158
159
160
161
162
163			`gen_verilog`
164			`104.0`
165			`none`
166			`common`
167			`./tools/verilog/gen_verilog`
168
169
170			`destination`
171	134	jt_eaton	`io_vga_def`
172	131	jt_eaton
173
174
175
176
177
178
179
180
181
182
183
184
185			`fs-common`
186
187
188
189			`../verilog/top.body`
190			`verilogSourcefragment`
191
192
193
194
195
196			`fs-sim`
197
198
199
200			`../verilog/copyright.v`
201			`verilogSourceinclude`
202
203
204
205
206
207	134	jt_eaton	`../verilog/common/io_vga_def`
208	131	jt_eaton	`verilogSourcemodule`
209
210
211
212			`mb`
213			`../verilog/io_vga_def_mb`
214			`verilogSourcemodule`
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233			`Hierarchical`
234
235
236			`spirit:library="io"`
237			`spirit:name="io_vga"`
238			`spirit:version="def.design"/>`
239
240
241
242
243			`verilog`
244
245
246			`spirit:library="Testbench"`
247			`spirit:name="toolflow"`
248			`spirit:version="verilog"/>`
249
250
251
252
253
254
255
256
257			`commoncommon`
258
259			`Verilog`
260
261
262			`fs-common`
263
264
265
266
267			`sim:Simulation:`
268
269			`Verilog`
270
271
272			`fs-sim`
273
274
275
276
277			`syn:Synthesis:`
278
279			`Verilog`
280
281
282			`fs-sim`
283
284
285
286
287
288
289			`doc`
290
291
292			`spirit:library="Testbench"`
293			`spirit:name="toolflow"`
294			`spirit:version="documentation"/>`
295
296			`:Documentation:`
297			`Verilog`
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312			`enable`
313			`wire`
314			`in`
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333			`mb`
334			`8`
335
336			`mb`
337			`0x00`
338
339
340			`mb_microbus`
341			`0x10`
342			`8`
343
344
345
346			`ascii_data`
347			`0x0`
348			`8`
349			`write-only`
350
351
352
353			`add_l`
354			`0x2`
355			`8`
356			`write-only`
357
358
359
360			`add_h`
361			`0x4`
362			`8`
363			`write-only`
364
365
366
367
368			`vadd_l`
369			`0x2`
370			`8`
371			`read-only`
372
373
374
375			`vadd_h`
376			`0x4`
377			`8`
378			`read-only`
379
380
381
382
383			`cntrl`
384			`0x6`
385			`8`
386			`read-write`
387
388
389
390
391
392
393			`char_color`
394			`0x8`
395			`8`
396			`read-write`
397
398
399
400
401
402			`back_color`
403			`0xa`
404			`8`
405			`read-write`
406
407
408
409
410			`cursor_color`
411			`0xc`
412			`8`
413			`read-write`
414
415
416
417
418
419
420
421
422
423
424
425